M68ICS08GR datasheet(85/408 Pages) FREESCALE

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Analog-to-Digital Converter (ADC)

I/O Registers

MC68HC908GR8 — Rev 4.0

Technical Data

MOTOROLA

Analog-to-Digital Converter (ADC)

5.8 I/O Registers

These I/O registers control and monitor ADC operation:

•

ADC status and control register (ADSCR)

•

ADC data register (ADR)

•

ADC clock register (ADCLK)

5.8.1 ADC Status and Control Register

Function of the ADC status and control register (ADSCR) is described

here.

COCO/IDMAS — Conversions Complete/Interrupt DMA Select Bit

When the AIEN bit is a logic 0, the COCO/IDMAS is a read-only bit

which is set each time a conversion is completed except in the

continuous conversion mode where it is set after the first conversion.

This bit is cleared whenever the ADSCR is written or whenever the

ADR is read.

If the AIEN bit is a logic 1, the COCO/IDMAS is a read/write bit which

selects either CPU or DMA to service the ADC interrupt request.

Reset clears this bit.

1 = Conversion completed (AIEN = 0)/DMA interrupt (AIEN = 1)

0 = Conversion not completed (AIEN = 0)/CPU interrupt (AIEN = 1)

CAUTION:

Because the MC68HC908GR8 does NOT have a DMA module, the

IDMAS bit should NEVER be set when AIEN is set. Doing so will mask

ADC interrupts and cause unwanted results.

Address:

$0003C

Bit 7

654321

Bit 0

Read:

COCO/

IDMAS

AIEN

ADCO

ADCH4

ADCH3

ADCH2

ADCH1

ADCH0

Write:

Reset:

00011111

Figure 5-2. ADC Status and Control Register (ADSCR)

Freescale Semiconductor, Inc.

For More Information On This Product,

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