M68ICS08GR datasheet(73/408 Pages) FREESCALE

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Resets and Interrupts

Interrupts

MC68HC908GR8 — Rev 4.0

Technical Data

MOTOROLA

Resets and Interrupts

•

Overflow bit (OVRF) — The OVRF bit is set if software does not

read the byte in the receive data register before the next full byte

enters the shift register. The error interrupt enable bit, ERRIE,

enables OVRF CPU interrupt requests. OVRF and ERRIE are in

the SPI status and control register.

4.4.2.8 SCI

SCI CPU interrupt sources:

•

SCI transmitter empty bit (SCTE) — SCTE is set when the SCI

data register transfers a character to the transmit shift register.

The SCI transmit interrupt enable bit, SCTIE, enables transmitter

CPU interrupt requests. SCTE is in SCI status register 1. SCTIE is

in SCI control register 2.

•

Transmission complete bit (TC) — TC is set when the transmit

shift register and the SCI data register are empty and no break or

idle character has been generated. The transmission complete

interrupt enable bit, TCIE, enables transmitter CPU interrupt

requests. TC is in SCI status register 1. TCIE is in SCI control

•

SCI receiver full bit (SCRF) — SCRF is set when the receive shift

receive interrupt enable bit, SCRIE, enables receiver CPU

interrupts. SCRF is in SCI status register 1. SCRIE is in SCI

control register 2.

•

Idle input bit (IDLE) — IDLE is set when 10 or 11 consecutive logic

1s shift in from the RxD pin. The idle line interrupt enable bit, ILIE,

enables IDLE CPU interrupt requests. IDLE is in SCI status

•

Receiver overrun bit (OR) — OR is set when the receive shift

was read from the SCI data register. The overrun interrupt enable

bit, ORIE, enables OR to generate SCI error CPU interrupt

requests. OR is in SCI status register 1. ORIE is in SCI control

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