M68ICS08GR datasheet(57/408 Pages) FREESCALE

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Low Power Modes

Exiting Wait Mode

MC68HC908GR8 — Rev 4.0

Technical Data

MOTOROLA

Low Power Modes

3.15 Exiting Wait Mode

These events restart the CPU clock and load the program counter with

the reset vector or with an interrupt vector:

•

External reset — A logic 0 on the RST pin resets the MCU and

loads the program counter with the contents of locations $FFFE

and $FFFF.

•

External interrupt — A high-to-low transition on an external

interrupt pin (IRQ pin) loads the program counter with the contents

of locations: $FFFA and $FFFB; IRQ pin.

•

Break interrupt — A break interrupt loads the program counter

with the contents of $FFFC and $FFFD.

•

Computer operating properly module (COP) reset — A timeout of

the COP counter resets the MCU and loads the program counter

with the contents of $FFFE and $FFFF.

•

Low-voltage inhibit module (LVI) reset — A power supply voltage

below the Vtripf voltage resets the MCU and loads the program

counter with the contents of locations $FFFE and $FFFF.

•

Clock generator module (CGM) interrupt — A CPU interrupt

request from the phase-locked loop (PLL) loads the program

counter with the contents of $FFF8 and $FFF9.

•

Keyboard module (KBI) interrupt — A CPU interrupt request from

the KBI module loads the program counter with the contents of

$FFDE and $FFDF.

•

Timer 1 interface module (TIM1) interrupt — A CPU interrupt

request from the TIM1 loads the program counter with the

contents of:

–

$FFF2 and $FFF3; TIM1 overflow

–

$FFF4 and $FFF5; TIM1 channel 1

–

$FFF6 and $FFF7; TIM1 channel 0

•

Timer 2 interface module (TIM2) interrupt — A CPU interrupt

request from the TIM2 loads the program counter with the

contents of:

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