M68ICS08GR datasheet(116/408 Pages) FREESCALE

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Clock Generator Module (CGMC)

Technical Data

MC68HC908GR8 — Rev 4.0

116

Clock Generator Module (CGMC)

MOTOROLA

1 = PLL interrupts enabled

0 = PLL interrupts disabled

PLLF — PLL Interrupt Flag Bit

This read-only bit is set whenever the LOCK bit toggles. PLLF

generates an interrupt request if the PLLIE bit also is set. PLLF

always reads as logic 0 when the AUTO bit in the PLL bandwidth

control register (PBWC) is clear. Clear the PLLF bit by reading the

PLL control register. Reset clears the PLLF bit.

1 = Change in lock condition

0 = No change in lock condition

NOTE:

Do not inadvertently clear the PLLF bit. Any read or read-modify-write

operation on the PLL control register clears the PLLF bit.

PLLON — PLL On Bit

This read/write bit activates the PLL and enables the VCO clock,

CGMVCLK. PLLON cannot be cleared if the VCO clock is driving the

base clock, CGMOUT (BCS = 1). (See Base Clock Selector Circuit.)

Reset sets this bit so that the loop can stabilize as the MCU is

powering up.

1 = PLL on

0 = PLL off

BCS — Base Clock Select Bit

This read/write bit selects either the crystal oscillator output,

CGMXCLK, or the VCO clock, CGMVCLK, as the source of the

CGMC output, CGMOUT. CGMOUT frequency is one-half the

frequency of the selected clock. BCS cannot be set while the PLLON

bit is clear. After toggling BCS, it may take up to three CGMXCLK and

three CGMVCLK cycles to complete the transition from one source

clock to the other. During the transition, CGMOUT is held in stasis.

(See Base Clock Selector Circuit.) Reset clears the BCS bit.

1 = CGMVCLK divided by two drives CGMOUT

0 = CGMXCLK divided by two drives CGMOUT

NOTE:

PLLON and BCS have built-in protection that prevents the base clock

selector circuit from selecting the VCO clock as the source of the base

clock if the PLL is off. Therefore, PLLON cannot be cleared when BCS

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