M68ICS08GR datasheet(124/408 Pages) FREESCALE

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Clock Generator Module (CGMC)

Technical Data

MC68HC908GR8 — Rev 4.0

124

Clock Generator Module (CGMC)

MOTOROLA

mode, such as when the PLL is first enabled and waiting for LOCK or

LOCK is lost.

7.8.2 Stop Mode

If the OSCSTOPENB bit in the CONFIG register is cleared (default),

then the STOP instruction disables the CGMC (oscillator and phase

locked loop) and holds low all CGMC outputs (CGMXCLK, CGMOUT,

and CGMINT).

If the STOP instruction is executed with the VCO clock, CGMVCLK,

divided by two driving CGMOUT, the PLL automatically clears the BCS

bit in the PLL control register (PCTL), thereby selecting the crystal clock,

CGMXCLK, divided by two as the source of CGMOUT. When the MCU

recovers from STOP, the crystal clock divided by two drives CGMOUT

and BCS remains clear.

If the OSCSTOPENB bit in the CONFIG register is set, then the phase

locked loop is shut off but the oscillator will continue to operate in stop

mode.

7.8.3 CGMC During Break Interrupts

The system integration module (SIM) controls whether status bits in

other modules can be cleared during the break state. The BCFE bit in

the SIM break flag control register (SBFCR) enables software to clear

status bits during the break state. (See SIM Break Flag Control

To allow software to clear status bits during a break interrupt, write a

logic 1 to the BCFE bit. If a status bit is cleared during the break state, it

remains cleared when the MCU exits the break state.

To protect the PLLF bit during the break state, write a logic 0 to the BCFE

bit. With BCFE at logic 0 (its default state), software can read and write

the PLL control register during the break state without affecting the PLLF

bit.

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