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M68ICS08GR датащи(PDF) 88 Page - Freescale Semiconductor, Inc |
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M68ICS08GR датащи(HTML) 88 Page - Freescale Semiconductor, Inc |
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88 / 408 page ![]() Analog-to-Digital Converter (ADC) Technical Data MC68HC908GR8 — Rev 4.0 88 Analog-to-Digital Converter (ADC) MOTOROLA 5.8.3 ADC Clock Register The ADC clock register (ADCLK) selects the clock frequency for the ADC. ADIV2–ADIV0 — ADC Clock Prescaler Bits ADIV2–ADIV0 form a 3-bit field which selects the divide ratio used by the ADC to generate the internal ADC clock. Table 5-2 shows the available clock configurations. The ADC clock should be set to approximately 1 MHz. ADICLK — ADC Input Clock Select Bit ADICLK selects either the bus clock or CGMXCLK as the input clock source to generate the internal ADC clock. Reset selects CGMXCLK as the ADC clock source. Address: $0003E Bit 7 654321 Bit 0 Read: ADIV2 ADIV1 ADIV0 ADICLK 0000 Write: Reset: 00000000 = Unimplemented Figure 5-4. ADC Clock Register (ADCLK) Table 5-2. ADC Clock Divide Ratio ADIV2 ADIV1 ADIV0 ADC Clock Rate 0 0 0 ADC input clock ÷ 1 0 0 1 ADC input clock ÷ 2 0 1 0 ADC input clock ÷ 4 0 1 1 ADC input clock ÷ 8 1 X X ADC input clock ÷ 16 X = don’t care Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com |
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