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Clock Generator Module (CGMC)

Interrupts

MC68HC908GR8 — Rev 4.0

Technical Data

MOTOROLA

Clock Generator Module (CGMC)

123

7.7 Interrupts

When the AUTO bit is set in the PLL bandwidth control register (PBWC),

the PLL can generate a CPU interrupt request every time the LOCK bit

changes state. The PLLIE bit in the PLL control register (PCTL) enables

CPU interrupts from the PLL. PLLF, the interrupt flag in the PCTL,

becomes set whether interrupts are enabled or not. When the AUTO bit

is clear, CPU interrupts from the PLL are disabled and PLLF reads as

logic 0.

Software should read the LOCK bit after a PLL interrupt request to see

if the request was due to an entry into lock or an exit from lock. When the

PLL enters lock, the VCO clock, CGMVCLK, divided by two can be

selected as the CGMOUT source by setting BCS in the PCTL. When the

PLL exits lock, the VCO clock frequency is corrupt, and appropriate

precautions should be taken. If the application is not frequency sensitive,

interrupts should be disabled to prevent PLL interrupt service routines

from impeding software performance or from exceeding stack

limitations.

NOTE:

Software can select the CGMVCLK divided by two as the CGMOUT

source even if the PLL is not locked (LOCK = 0). Therefore, software

should make sure the PLL is locked before setting the BCS bit.

7.8 Special Modes

The WAIT instruction puts the MCU in low power-consumption standby

modes.

7.8.1 Wait Mode

The WAIT instruction does not affect the CGMC. Before entering wait

mode, software can disengage and turn off the PLL by clearing the BCS

and PLLON bits in the PLL control register (PCTL) to save power. Less

power-sensitive applications can disengage the PLL without turning it

off, so that the PLL clock is immediately available at WAIT exit. This

would be the case also when the PLL is to wake the MCU from wait

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