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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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M68ICS08GR датащи(PDF) 62 Page - Freescale Semiconductor, Inc |
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M68ICS08GR датащи(HTML) 62 Page - Freescale Semiconductor, Inc |
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62 / 408 page  Resets and Interrupts Technical Data MC68HC908GR8 — Rev 4.0 62 Resets and Interrupts MOTOROLA 4.3.2 External Reset A logic 0 applied to the RST pin for a time, tIRL, generates an external reset. An external reset sets the PIN bit in the SIM reset status register. 4.3.3 Internal Reset Sources: • Power-on reset (POR) • Computer operating properly (COP) • Low-power reset circuits • Illegal opcode • Illegal address All internal reset sources pull the RST pin low for 32 CGMXCLK cycles to allow resetting of external devices. The MCU is held in reset for an additional 32 CGMXCLK cycles after releasing the RST pin. Figure 4-1. Internal Reset Timing 4.3.3.1 Power-On Reset A power-on reset is an internal reset caused by a positive transition on the VDD pin. VDD at the POR must go completely to 0 V to reset the MCU. This distinguishes between a reset and a POR. The POR is not a brown- out detector, low-voltage detector, or glitch detector. RST PIN PULLED LOW BY MCU INTERNAL 32 CYCLES 32 CYCLES CGMXCLK RESET Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com |
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