OR3LP26B datasheet(75/184 Pages) AGERE

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Lucent Technologies Inc.

Data Sheet

ORCA OR3LP26B FPSC

March 2000

Embedded Master/Target PCI Interface

Lucent Technologies Inc.

PCI Bus Core Detailed Description Quad Port (continued)

Table 23. Embedded Core/FPGA Interface Signals (continued)

Symbol

I/O

Description

trlastcycn

Target Read Last Data Cycle. This active-low signal is asserted to indicate that

the accompanying Target read data is the final data for this operation. When more

than one cycle is required to transfer a complete data word, this signal is only

valid on the last cycle. During a read burst, trlastcycn may remain inactive for

longer than it is required to complete the data transfer. If this occurs, the FPGA

Target should continue to write data into the Target read FIFOs unless the incre-

mented address crosses the address decode space of the FPGA Target. The

address should be incremented by a double word as long as trlastcycn is inac-

tive.

This signal is synchronous to fclk.

trburstpendn

Target Read Burst Data Availability Pending Flag. This active-low signal

directs the PCI core not to immediately disconnect when the Target read FIFO

becomes empty, but rather to insert PCI bus wait-states (up to the maximum

allowed, and then disconnect). Once asserted, this signal needs to remain

asserted for a minimum or two pciclk periods.

This signal must be synchronous to pciclk.

Miscellaneous Signals

pci_intan

PCI Interrupt Request. This active-low signal is used to generate a PCI bus

interrupt and is forwarded by the PCI core as intan onto the PCI bus. Once

asserted, this signal needs to remain asserted for a minimum of two pciclk

cycles.

This signal must be synchronous to pciclk.

fclk1

fclk2

FPGA Clock 1 and 2. Clocks for use by the PCI core for Master and Target

FIFOs. When the PCI clock domain extends into the FPGA, the FPGA may

reroute the PCI clock back into fclk1 or fclk2. External or user-defined clocks may

also be used. The signals fclk1 and fclk2 must be the same clock in dual-port

mode.

pciclk

PCI Clock. The signal pciclk is synchronous to clk and may be used by the

FPGA logic.

pci_rstn

PCI Reset for Use by the FPGA Logic. This active-low signal indicates that a

PCI bus reset was received from the PCI bus (rstn).

fpga_syserror

System Error. This active-high signal is used by the FPGA to generate a system

error on the PCI bus. This is passed to the PCI bus as serrn.

This signal must be synchronous to pciclk.

pci_64bit

PCI Bus in 64-Bit Mode. This active-high signal indicates that the PCI core

detected that it is connected as a 64-bit agent to the PCI bus. This is the result of

detecting PCI signal req64n as active (low) on the inactive-going (rising) edge of

PCI signal rstn. Note that this does not imply that any particular transaction is

64-bit, since each transaction is individually negotiated using PCI signals req64n

and ack64n.

This signal is synchronous to pciclk.

fifo_sel

FIFO Select. An active-high signal that is valid in the dual-port modes to select

either Master read data (fifo_sel = 0) or Target write data (fifo_sel = 1).

This signal must be synchronous to fclk.

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