OR3LP26B datasheet(88/184 Pages) AGERE

88 / 184 page

Lucent Technologies Inc.

ORCA OR3LP26B FPSC

Data Sheet

Embedded Master/Target PCI Interface

March 2000

Lucent Technologies Inc.

PCI Bus Core Detailed Description

Quad Port (continued)

Master (FPGA Initiated) Write

Operation Setup

In order to initiate a PCI Master write operation, the

FPGA application must supply the required information

in the specific order prescribed in Table 36. A master

command word and address must be accompanied by

assertion of the enable maenn. The definition of the

Master command word is shown in Table 25. The

FPGA application can use the value returned on bus

mstatecntr, the Master write counter’s present value,

to determine the counter’s next state, using the state

diagram for the particular operation being executed.

The counter’s next state must be determined because

the FPGA application must supply the data to the PCI

core that corresponds to the counter value being sent

from the core to the FPGA.

Master State Counter

The PCI core provides a state counter,

mstatecntr[2:0], that informs the FPGA of the current

state of the PCI core's Master state counter. This state

counter determines what data is currently being pro-

vided by the PCI core or expected from the FPGA

application. This state counter transitions from one

state to another in a predictable fashion, and thus, it is

not strictly necessary to transmit its value to the FPGA.

Nonetheless, the value on bus mstatecntr can be used

to minimize FPGA logic or verify proper operation.

The data provided by the PCI core to the FPGA appli-

cation on bus mrdata is accompanied by a value on bus

mstatecntr. This value can be directly used by the

FPGA application to determine the proper use of that

data. This eliminates the need for logic in the FPGA to

duplicate this state counters in this case.

The data required from the FPGA application by the

PCI core on bus mwdata is also defined by the value

on bus mstatecntr. However, the state counter value is

being sent to the FPGA in the same cycle that the data

must be sent from the FPGA. Therefore, the FPGA

application must build its own copy of the state counter

value in this case. The value provided by the PCI core

can be used as the previous value, or it can be used to

verify the proper operation of the FPGA application's

logic.

Table 25 lists the values of the state counter mstate-

cntr and the appropriate accompanying data.

Data Transfer

The FPGA application begins supplying the write data

by deasserting maenn and asserting mwdataenn. On

every cycle that mwdataenn is asserted, the PCI core

clocks data and its associated byte enables into the

Master write FIFO (64 deep by 36 bits wide in 32-bit

PCI mode; 32 deep by 72 bits wide in 64-bit PCI mode)

via bus mwdata.

FIFO Full/Almost Full

When the Master write FIFO contains four or fewer

empty locations, the PCI core asserts mw_afulln, the

almost full indicator. This allows some latency to exist

in the FPGA’s response without risking overfilling the

FIFO. When all locations in the Master write FIFO are

full, the PCI core asserts mw_fulln, the FIFO full indi-

cator. Since data can be simultaneously written to and

read from the Master write FIFO, both mw_afulln and

mw_fulln can change states in either direction multiple

times in the course of a burst transfer.

FIFO Empty

In addition to the full and almost full signals that report

when the Master write FIFO is currently unable to

receive data from the FPGA application, the PCI core

also provides the FIFO's empty signal. During a master

write burst transaction, the master write FIFO may go

empty, especially if the user side application is slow at

filling the FIFO. When this condition occurs, the master

will insert wait-states continuously until another word

(or the last word) is written into the FIFO and will not

terminate the transaction. On the target side, if the tar-

get is ready to accept more data, it will have trdyn

asserted which will disable it from terminating the

transaction as well. This can create a deadlock condi-

tion on the PCI bus. If the user application cannot sup-

ply any more data, and wishes to terminate the burst,

additional FPGA logic must be incorporated to detect

and accomplish the termination. The way to terminate

the transaction is to provide one last piece of data

(either real data or a dummy data word with all byte

enables disabled) along with mwlastcycn asserted.

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