OR3LP26B datasheet(35/184 Pages) AGERE

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Lucent Technologies Inc.

Data Sheet

ORCA OR3LP26B FPSC

March 2000

Embedded Master/Target PCI Interface

Lucent Technologies Inc.

PCI Bus Core Detailed Description Dual Port (continued)

Embedded Core/FPGA Interface Operation Summary

The following sections describe the FIFO bus operation, which is the interface between the embedded core and the

FPGA logic. Several configurations are possible for the FIFO bus, and the signal definitions can change for differ-

ent modes. Tables are provided to define the modes, the signal definitions, and the states of each operation for

each mode.

Table 17 is an index to the state tables and timing figures provided for each of the operational modes of the FPGA

interface to the PCI core. Each of these operations is detailed on the pages shown in the table.

Table 17. Index to State Sequence Tables

* 64-bit address supplied.

† 32-bit address supplied.

‡ The FPGA interface does not participate in Target configuration operations.

Master/

Target

PCI Bus

Mode

Transaction Type

Single/Burst and

Delayed/Not Delayed

PCI Bus Timing

Figure Number

State Table

FPGA Bus

Timing Figure

Number

Master

Write

Config, Memory, I/O

Nonburst

Figure 3

Table 18

Figure 2

Burst

Figure 5

Figure 4

Read

Config, Memory, I/O

Nonburst

Figure 7

Table 19*

Table 20†

Figure 6

Burst

Figure 9

Figure 8

Target

Write

Config

Nonburst

Figure 10

Table 21

‡

I/O

Delayed

Figure 11

Figure 13

Memory, I/O

Nonburst, Not Delayed

Figure 12

Figure 15

Memory

Burst

Figure 14

Read

Config

Nonburst

Figure 16

Table 22

‡

I/O

Delayed

Figure 17

Figure 20

Not Delayed

Figure 18

Memory

Nonburst

Figure 21

Nonburst Delayed

Figure 19

Burst

Figure 24

Figure 23

Burst Delayed

Figure 22

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