OR3LP26B datasheet(91/184 Pages) AGERE

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Lucent Technologies Inc.

Data Sheet

ORCA OR3LP26B FPSC

March 2000

Embedded Master/Target PCI Interface

Lucent Technologies Inc.

PCI Bus Core Detailed Description Quad Port (continued)

Master Write, Burst Transaction

Figure 28 (FPGA bus) and Figure 26 (PCI bus) show the timing of a 4-Quadword Master write burst transaction.

Operation is similar to that in the previous Master write, nonburst transaction, but extra data is supplied by the

FPGA application. In Figure 28, the transaction is initiated by the FPGA application asserting Master address

enable (maenn), while providing the command word and the lower DWORD address on bus mwdata. On the sec-

ond clock, for 64-bit addressing, the upper DWORD address is supplied along with mwlastcycn. On the third

through tenth clocks, maenn is deasserted, the Master write data enable (mwdataenn) is asserted, and eight

DWORDs of data are provided on bus mwdata. On the tenth clock, mwlastcycn is asserted along with the last

DWORD of data. Since the protocol for providing start-up data is fixed for a specific operation, the FPGA applica-

tion can be preprogrammed with the sequence, or can use the value of the Master state counter (mstatecntr) to

assist in determination of the next required DWORD of information. The PCI core knows that this is a burst opera-

tion because the FPGA application deasserts the Master write burst signal (mwlastcycn) during all but the final

data transfer cycle. Execution begins on the PCI bus, as shown in Figure 26. If the Master write PCI bus hold signal

(mwpcihold) is inactive, PCI bus activity will begin when the Master write FIFO goes nonempty; otherwise, the PCI

bus activity will wait until all data is loaded, as in this case, or the FIFO goes full. Execution begins on the PCI bus,

as shown in Figure 26.

5-8848(F).a

Figure 26. Master Write 32-Byte Burst (PCI Bus, 64-Bit)

ADRS

CMD

BE0

BE1

BE2

BE3

clk

framen

c_ben

irdyn

devseln

trdyn

stopn

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