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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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OR3LP26B датащи(PDF) 69 Page - Agere Systems |
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OR3LP26B датащи(HTML) 69 Page - Agere Systems |
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69 / 184 page  Lucent Technologies Inc. 69 Data Sheet ORCA OR3LP26B FPSC March 2000 Embedded Master/Target PCI Interface Lucent Technologies Inc. PCI Bus Core Detailed Description Dual Port (continued) Target Read Memory Burst, No Delayed Transaction Figure 24 (PCI bus) and Figure 23 (FPGA bus) show the timing for a Target memory burst read of four Quadwords handled as a nondelayed transaction. Figure 24 shows the timing on the PCI interface is similar to that of an I/O read (Figure 18) except that stop is not asserted here to cause disconnect with data, but rather the operation is free to continue since it is allowed to complete on the source (PCI) bus before it completes on the destination (FPGA) bus. 5-8861(F).a Figure 24. Target Read Memory Burst, No Delayed (PCI Bus, 32-Bit) Table 22. Dual-Port Target Read * treqn is deasserted high on the last data Quadword. † twlastcycn is asserted low on the last data Quadword. tstatecntr Next State of tstatecntr Description Bus treqn trdataenn twlastcycn taenn trlastcycn 00 Idle — 1 1 1 1 1 0 4 Address[63: 0] datatofpgax[7:0] datatofpga[63:0] 01 1 0 0 4 4 or 0 Data[63:0] datafmfpga[63:0] 1* 0 0† 11 T0 T1 T2 T3 Tn0 Tn1 Tn2 Tn3 Tn4 Tn5 Tn6 X ADRS X X D0 D1 D2 D3 X X CMD BE0 BE0 BE1 BE2 BE3 clk framen ad c_ben irdyn devseln trdyn stopn |
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