OR3LP26B datasheet(12/184 Pages) AGERE

12 / 184 page

Lucent Technologies Inc.

ORCA OR3LP26B FPSC

Data Sheet

Embedded Master/Target PCI Interface

March 2000

Lucent Technologies Inc.

OR3LP26B Overview (continued)

OR3LP26B PCI Bus Core Overview

The OR3LP26B embedded core comprises a PCI bus

interface with independent Master and Target control-

lers, FIFO memories and control logic for data buffer-

ing, a dual-/quad-port interface to the FPGA logic

which performs data packing and multiplexing, and

logic to support embedded core and FPGA configura-

tion. Each of these areas is briefly described in the fol-

lowing paragraphs. A detailed description of all of the

features and functionality of the OR3LP26B embedded

core is provided in the next section.

PCI Bus Interface

The OR3LP26B PCI bus interface is compliant to Revi-

sion 2.2 of the PCI Local Bus specification. It is capable

of no-wait-state, full-burst operation at all of the

rate/data width combinations described in Table 2 as

well as at a 50 MHz specification that provides a speed

increase over the 33 MHz specification and a larger

bus loading capability than the 66 MHz specification.

The OR3LP26B operates in either the 3.3 V or 5 V PCI

signaling environment and is automatically configured

for the appropriate environment by a PCI bus vio pin.

Independent Master and Target controllers are pro-

vided for use in systems requiring Master/Target or Tar-

get only operation. Six 32-bit base address registers

(BARs) are provided for choosing the address space of

the PCI device, and these six registers can be com-

bined in pairs to produce 64-bit BARs. Dual address

cycles are supported in both 32-bit and 64-bit address-

ing modes. The BARs work in either the I/O or the

memory space of the device, and can be configured as

prefetchable or nonprefetchable.

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