OR3LP26B datasheet(22/184 Pages) AGERE

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ORCA OR3LP26B FPSC

Data Sheet

Embedded Master/Target PCI Interface

March 2000

Lucent Technologies Inc.

PCI Bus Core Detailed Description Dual Port (continued)

Table 8. Embedded Core/FPGA Interface Signals (continued)

Symbol

I/O

Description

m_ready

Master Logic Ready. This active-high signal indicates that the Master logic

interfacing to the FPGA logic is ready. This signal will be inactive during PCI bus

reset or Master FIFO clears.

This signal is synchronous to fclk.

mcmd[3:0]

Master Command Code. Command code for the current Master read/write

operation. Refer to Table 10 on page 30.

This signal must be synchronous to fclk.

Master Write Data FIFO Signals

mwdataenn

Master Write FIFO Data Enable. This active-low signal enables the registering

of bus datafmfpga during Master write operations into the PCI core Master

write data FIFOs on the rising edge of the Master FIFO clock signal. The signal

mwdataenn should not be asserted when the Master write data FIFOs are full,

or data may be lost.

This signal must be synchronous to fclk.

mwpcihold

Master Write PCI Bus Hold. During burst transfers on the PCI bus, this signal

delays the start of the transfer on the PCI bus, allowing the FPGA application to

fill the FIFO. The transaction will begin when mwpcihold is deasserted or the

FIFO becomes full. When asserted, mwpcihold must be held low for a mini-

mum of two pciclk periods.

This signal must be synchronous to pcilk.

mw_fulln

Master Write Data FIFO Full Flag. This active-low signal indicates that the

Master write data FIFOs are full.

This signal is synchronous to fclk.

mw_afulln

Master Write Data FIFO Almost Full Flag. This active-low signal indicates that

only four more empty locations remain in the Master write data FIFOs.

This signal is synchronous to fclk.

mw_emptyn

Master Write Data FIFO Empty Flag. This active-low signal indicates that the

Master write data FIFO is empty. Refer to Master write description on signal

usage.

This signal is synchronous to pciclk.

mwlastcycn

Master Write Last Data Cycle. This active-low signal has two functions:

a. It is asserted low to indicate that the accompanying 32/64 bits of Master read

or write address information is the final portion being sent. It can also be

asserted prior to any address portion being sent, indicating that the previous

address is to be used.

b. It is asserted low to indicate that the accompanying master write data is the

final data for this operation. When more than one cycle is required to transfer

a complete data word, this signal is only valid on the last cycle.

This signal must be synchronous to fclk.

Master Read Data FIFO Signals

mrdataenn

Master Read FIFO Data Output Enable. This active-low signal enables the

data from the PCI core Master read data FIFOs onto bus datatofpga during

Master read operations on the rising edge of the Master FIFO clock signal. Valid

data will be read from the FIFO whenever it is not empty.

This signal must be synchronous to fclk.

mr_emptyn

Master Read Data FIFO Empty. This active-low signal indicates that the Mas-

ter read data FIFOs of the PCI core are empty.

This signal is synchronous to fclk.

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