OR3LP26B datasheet(34/184 Pages) AGERE

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ORCA OR3LP26B FPSC

Data Sheet

Embedded Master/Target PCI Interface

March 2000

Lucent Technologies Inc.

PCI Bus Core Detailed Description Dual Port (continued)

Table 16. Dual-Port FIFO Packing/Unpacking, Case 2, FPGA Side

Note: PCI addresses in parentheses are not actually sent across the PCI bus during a burst. They are used for illustrative purposes only.

Dummy words are unknown data words in the FIFOs with their byte enables disabled.

Embedded Core/FPGA Interface Operation

Target Address Holding Register and BAR Number Indicator

The PCI core provides two features that reduce overhead on setup of Target transfers.

First, the PCI core’s Target control logic detects the page size of the base address register (BAR) that matched the

current PCI address, and only transfers the address bytes necessary to send the page address, and not the virtual

address of the page, to the FPGA application. The bar bus is synchronous to pciclk, so it must be qualified with

treqn.

Second, the PCI core utilizes an optional address holding register so that only the least significant portion of the

address that is different from the previous address is sent to the FPGA application. Utilization of this feature usually

reduces the amount of address that must be transferred, but may require that the FPGA application build a copy of

the holding register in order to reconstruct the address. For this reason, this feature is optional and can be disabled

via a bit in the FPGA configuration manager.

Interrupt Request and System Error Generation

Two additional signals are available on the user side interface to request an interrupt on intan (pci_intan) and force

a system error on the PCI serrn pin (fpga_syserror). The pci_intan signal may be asserted low at any time. It is

not directly tied to any bus cycle. The fpga_syserror, as well, may be asserted high at any time. The serrn signal

will be subsequently asserted low during the next PCI transaction to this device. In generating pci_intan and

fpga_syserror, keep in mind that both signals need to be synchronous to pciclk.

Working in 32-bit and 64-bit Modes

The OR3LP26B works equally well in 32-bit and 64-bit PCI systems. In a 64-bit system, it is required that, during

reset, the host assert req64n low indicating that the bus width is 64 bits. The core will evaluate this signal at reset,

and automatically configure itself in either 32-bit or 64-bit mode. When configured in 32-bit mode, the core will

3-state all upper PCI bus pins and apply a weak pull-up.

32-Bit Transfers in a 64-bit System

Although designed as a 64-bit interface, the OR3LP26B also works efficiently in 32-bit mode. For single 32-bit

transfers, the core will perform a 32-bit PCI transfer. For burst transactions, the core will attempt 64-bit transfers,

and then back down to 32-bit mode if ack64n was not received. In general, the core will perform the PCI bus trans-

action that is most efficient on the bus.

Master Write FIFO Slot

FIFO Data Bits 63:32

FIFO Data Bits 31:0

FIFO Byte Enables

(Active-Low)

datatofpga[63:0]

datatofpgax[7:0]

32-bit Word2

32-bit Word1

00000000

32-bit Word4

32-bit Word3

00000000

Dummy Word

32-bit Word5

FFFF0000

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