OR3LP26B datasheet(9/184 Pages) AGERE

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Lucent Technologies Inc.

Data Sheet

ORCA OR3LP26B FPSC

March 2000

Embedded Master/Target PCI Interface

Lucent Technologies Inc.

Description (continued)

PIC Logic

The Series 3 PIC addresses the demand for ever-

increasing system clock speeds. Each PIC contains

four programmable inputs/outputs (PIOs) and routing

resources. On the input side, each PIO contains a fast-

capture latch that is clocked by an ExpressCLK. This

latch is followed by a latch/FF that is clocked by a sys-

tem clock from the internal general clock routing. The

combination provides for very low setup requirements

and zero hold times for signals coming on-chip. It may

also be used to demultiplex an input signal, such as a

multiplexed address/data signal, and register the sig-

nals without explicitly building a demultiplexer. Two

input signals are available to the PLC array from each

PIO, and the

ORCA Series 2 capability to use any input

pin as a clock or other global input is maintained.

On the output side of each PIO, two outputs from the

PLC array can be routed to each output flip-flop, and

logic can be associated with each I/O pad. The output

logic associated with each pad allows for multiplexing

of output signals and other functions of two output sig-

nals.

The output FF, in combination with output signal multi-

plexing, is particularly useful for registering address

signals to be multiplexed with data, allowing a full clock

cycle for the data to propagate to the output. The I/O

buffer associated with each pad is the same as the

ORCA Series 3 buffer.

System Features

The Series 3 also provides system-level functionality by

means of its dual-use microprocessor interface (MPI)

and its innovative programmable clock manager

(PCM). These functional blocks allow for easy glueless

system interfacing and the capability to adjust to vary-

ing conditions in today’s high-speed systems. Since

these and all other Series 3 features are available in

every Series 3+ FPSC, they can also interface to the

embedded core providing for easier system integration.

Routing

The abundant routing resources of

ORCA Series 3

FPGA logic are organized to route signals individually

or as buses with related control signals. Clocks are

routed on a low-skew, high-speed distribution network

and may be sourced from PLC logic, externally from

any I/O pad, or from the very fast ExpressCLK pins.

ExpressCLKs may be glitchlessly and independently

enabled and disabled with a programmable control sig-

nal using the new StopCLK feature. The improved PIC

routing resources are now similar to the patented intra-

PLC routing resources and provide great flexibility in

moving signals to and from the PIOs. This flexibility

translates into an improved capability to route designs

at the required speeds when the I/O signals have been

locked to specific pins.

Configuration

The FPGA logic’s functionality is determined by internal

configuration RAM. The FPGA logic’s internal initializa-

tion/configuration circuitry loads the configuration data

at powerup or under system control. The RAM is

loaded by using one of several configuration modes,

including serial EEPROM, the microprocessor inter-

face, or the embedded function core.

Boundary Scan

Boundary scan is implemented in the OR3LP26B

device as with any of the OR3LXXB family of parts. The

PCI core side of the device contains the same bound-

ary-scan registers. After performing a boundary-scan

test, it is highly recommended that the device be reset

through the PCI rstn pin. This reset will clear out any

PCI core internal registers that may have been set dur-

ing the boundary-scan tests.

More Series 3 Information

For more information on Series 3 FPGAs, please refer

to the Series 3 FPGA data sheet, available on the

ORCA worldwide website or by contacting Lucent

Technologies as directed on the back of this data

sheet.

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