OR3LP26B datasheet(33/184 Pages) AGERE

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Lucent Technologies Inc.

Data Sheet

ORCA OR3LP26B FPSC

March 2000

Embedded Master/Target PCI Interface

Lucent Technologies Inc.

PCI Bus Core Detailed Description Dual Port (continued)

Understanding FIFO Packing/Unpacking

In dual-port mode, the interface from the core to the FPGA is always 64 bits wide. However, data packing through

the FIFOs will differ depending on whether the transfers on the PCI bus are 32 bits or 64 bits. The following discus-

sions pertain to target write or master read operations where data will be read from the FIFOs.

64-bit Transfers: Since the FIFOs are always in 64-bit mode, the data will flow through without any repacking.

Keep in mind that 64-bit transfers must start on a Quadword aligned address (AD2 = 0).

32-bit Transfers: The FIFOs are always in 64-bit mode, so depending upon what address the transfer begins,

the data coming out of the FIFOs will be packed differently. The following two cases provide examples with differ-

ent starting addresses and word counts. Case 1 is also true for Master read operations.

Case 1: Target write burst, 32-bit. Even 32-bit starting address, and even number of 32-bit words transferred on the

PCI bus.

Table 13. Dual-Port FIFO Packing/Unpacking, Case 1, PCI Side

Table 14. Dual-Port FIFO Packing/Unpacking, Case 1, FPGA Side

Note: PCI addresses in parentheses are not actually sent across the PCI bus during a burst. They are used for illustrative purposes only.

Dummy words are unknown data words in the FIFOs with their byte enables disabled.

Case 2: Target write burst, 32-bit. Even 32-bit starting address, odd number of 32-bit words transferred on the PCI

bus.

Table 15. Dual-Port FIFO Packing/Unpacking, Case 2, PCI Side

PCI Address

PCI Data

PCI Byte Enables

(Active-Low)

00001000

32-bit Word1

0000

(00001004)

32-bit Word2

0000

(00001008)

32-bit Word3

0000

(0000100C)

32-bit Word4

0000

(00001010)

32-bit Word5

0000

(00001014)

32-bit Word6

0000

Master Write FIFO Slot

FIFO Data Bits 63:32

FIFO Data Bits 31:0

FIFO Byte Enables

(Active-Low)

datatofpga[63:0]

datatofpgax[7:0]

32-bit Word2

32-bit Word1

00000000

32-bit Word4

32-bit Word3

00000000

32-bit Word6

32-bit Word5

00000000

PCI Address

PCI Data

PCI Byte Enables

(Active-Low)

00001000

32-bit Word1

0000

(00001004)

32-bit Word2

0000

(00001008)

32-bit Word3

0000

(0000100C)

32-bit Word4

0000

(00001010)

32-bit Word5

0000

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