OR3LP26B datasheet(56/184 Pages) AGERE

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ORCA OR3LP26B FPSC

Data Sheet

Embedded Master/Target PCI Interface

March 2000

Lucent Technologies Inc.

PCI Bus Core Detailed Description Dual Port (continued)

Target Write Memory Burst Transaction

Figure 14 (PCI bus) and Figure 15 (FPGA bus) show the timing for a Target memory write burst of four Quadwords.

The timing on the PCI interface (Figure 14) is typical for a medium-speed decode Target. Note that trdyn is

asserted at the earliest possible time, which is concurrent with assertion of devseln. In the example of a four Quad-

word burst, the FIFO is not filled, so execution continues to completion. This would also be the case for a burst of

any length when the FPGA application is capable of unloading the FIFO as fast as the PCI interface is loading it. If

the Target write FIFO becomes full, the PCI core Target will disconnect without data on the first data word it cannot

accept.

The timing on the FPGA interface (Figure 15) shows that the first indication to the FPGA application that a new

operation has begun is the assertion of target request (treqn), together with the new command on bus

tcmd. The FPGA application responds by asserting target address enable (taenn) and accepting the address on

bus datatofpga. This is followed by deassertion of taenn, assertion of Target write data enable (twdataenn), and

the receiving of the data on bus datatofpga. The FPGA application is informed that the last 64-bit data is being

presented when Target write burst (twlastcycn) is asserted.

5-8855(F).a

Figure 14. Target Memory Write 32-Byte Burst (PCI Bus, 64-Bit)

ADDRESS

CMD

BE0

BE1

BE2

BE3

clk

framen

c_ben

irdyn

devseln

trdyn

stopn

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