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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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OR3LP26B датащи(PDF) 93 Page - Agere Systems |
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OR3LP26B датащи(HTML) 93 Page - Agere Systems |
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93 / 184 page  Lucent Technologies Inc. 93 Data Sheet ORCA OR3LP26B FPSC March 2000 Embedded Master/Target PCI Interface Lucent Technologies Inc. PCI Bus Core Detailed Description Quad Port (continued) 5-8840(F).a Figure 28. Master Write 32-Byte Burst (FPGA Bus, Quad-Port, 64-Bit Address) Table 36. Quad-Port Master Write * mwlastcycn is only 0 during the last data DWORD sent. Notes: For 32-bit addressing, state 1 is absent. For 32-bit data, state 5 is absent. mstatecntr Next State of mstatecntr Description Bus maenn mwdataenn mwlastcycn 00Idle — 1 1 1 0 1 Address[31:0] mwdata[35:0] 0 1 1 1 4 Address[63:32] mwdata[35:0] 0 1 0 4 5 or 0 Data[31:0], BE[3:0] mwdata[35:0] 1 0 1 5 4 or 0 Data[63:32], BE[7:4] mwdata[35:0] 1 0 0* T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 X 0 1 4 5 4 5 4 5 4 5 0 X CMD X X ADRS-L ADRS-U D0 D1 D2 D3 D4 D5 D6 D7 X fclk m_ready ma_fulln mstatecntr mcmd mwdata maenn mwdataenn mwlastcycn mw_fulln mw_afulln mwpcihold |
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