OR3LP26B datasheet(87/184 Pages) AGERE

87 / 184 page

Lucent Technologies Inc.

Data Sheet

ORCA OR3LP26B FPSC

March 2000

Embedded Master/Target PCI Interface

Lucent Technologies Inc.

PCI Bus Core Detailed Description Quad Port (continued)

Interrupt Request and System Error Generation

Two additional signals are available on the user side interface to request an interrupt on intan (pci_intan) and

force a system error on the PCI serrn pin (fpga_syserror). The pci_intan signal may be asserted low at any time.

It is not directly tied to any bus cycle. The fpga_syserror, as well, may be asserted high at any time. The serrn will

be subsequently asserted low during the next PCI transaction to this device. In generating pci_intan and

fpga_syserror, keep in mind that both signals need to be synchronous to pciclk.

Working in 32- and 64-bit Modes

The OR3LP26B works equally well in 32-bit and 64-bit PCI systems. In a 64-bit system, it is required that, during

reset, the host assert req64n low indicating that the bus width is 64 bits. The core will evaluate this signal at reset,

and automatically configure itself in either 32-bit or 64-bit mode. When configured in 32-bit mode, the core will 3-

state all upper PCI bus pins and apply a weak pull-up.

32-bit Transfers in a 64-bit System

Although designed as a 64-bit interface, the OR3LP26B also works efficiently in 32-bit mode. For single 32-bit

transfers, the core will perform a 32-bit PCI transfer. For burst transactions, the core will attempt 64-bit transfers,

and then back down to 32-bit mode if ack64n was not received. In general, the core will perform the PCI bus trans-

action that is most efficient on the bus.

Embedded Core/FPGA Interface Operation Summary

The following sections describe the FIFO bus operation, which is the interface between the embedded core and the

FPGA logic. Several configurations are possible for the FIFO bus, and the signal definitions can change for differ-

ent modes. Tables are provided to define the modes, the signal definitions, and the states of each operation for

each mode.

Table 35 is an index to the state tables and timing figures provided for each of the operational modes of the FPGA

interface to the PCI core. Each of these operations is detailed on the pages shown in the table.

Table 35. Index to State Sequence Tables

* Duplicate burst length and 16-bit address.

† 64-bit address supplied.

‡ 32-bit address supplied.

§ The FPGA interface does not participate in Target configuration operations.

Master/

Target

PCI Bus

Mode

Transaction Type

Single/Burst and Delayed/

Not Delayed

PCI Bus Timing

Figure Number

State Table

FPGA Bus Timing

Figure Number

Master

Write

Config,

Memory, I/O

Nonburst

Figure 25

Table 36

Figure 27

Burst

Figure 26

Figure 28

Read

Config,

Memory, I/O

Nonburst

Figure 29

Table 37*†

Table 38‡

Figure 30

Burst

Figure 31

Figure 32

Target

Write

Config

Nonburst

Figure 33

Table 39

I/O

Delayed

Figure 34

Figure 36

Memory, I/O

Nonburst, Not Delayed

Figure 35

Figure 38

Memory

Burst

Figure 37

Read

Config

Nonburst

Figure 39

Table 40

I/O

Delayed

Figure 40

Figure 43

Not Delayed

Figure 41

Memory

Nonburst

Figure 44

Nonburst Delayed

Figure 42

Burst

Figure 47

Figure 46

Burst Delayed

Figure 45

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