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PCA9620 датащи(PDF) 14 Page - NXP Semiconductors |
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PCA9620 датащи(HTML) 14 Page - NXP Semiconductors |
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14 / 71 page ![]() PCA9620 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 1 — 9 December 2010 14 of 71 NXP Semiconductors PCA9620 Universal LCD driver for low multiplex rates The host microprocessor or microcontroller maintains the 2 line I2C-bus communication channel with the PCA9620. The appropriate biasing voltages for the multiplexed LCD waveforms are generated internally. The only other connections required to complete the system are the power supplies (VDD1, VDD2, VSS, VLCD), the external capacitors, and the LCD panel selected for the application. The minimum recommended values for external capacitors on VDD1, VDD2, and VLCD are nominal 100 nF. When using bigger capacitors, especially on the VLCD, the generated ripple will be consequently smaller, however it will take longer for the internal charge pump to first reach the target VLCD voltage. In the case that VDD1 and VDD2 are connected externally, the capacitors on VDD1 and VDD2 can be replaced by a single capacitor with a minimum value of 200 nF. Remark: In the case of insufficient decoupling, ripple of VDD1 and VDD2 will create additional VLCD ripple. The ripple on VLCD can be reduced by making the VSS connection as low-ohmic as possible. Excessive ripple on VLCD may give rise to flicker on the display. 7.3 Start-up and shut-down 7.3.1 Power-On Reset (POR) At power-on the PCA9620 resets to starting conditions as follows: 1. All backplane outputs are set to VSS. 2. All segment outputs are set to VSS. 3. Selected drive mode is: 1:8 with 1 ⁄ 4 bias. 4. Input and output bank selectors are reset. 5. The I2C-bus interface is initialized. 6. The data pointer is cleared (set logic 0). 7. The Internal oscillator is running; no clock signal is available on pin CLK; pin CLK is in 3-state. 8. Temperature measurement is enabled. VDD1 from 2.5 V to 5.5 V, VDD2 from 2.5 V to 5.5 V and VLCD from 2.5 V to 9.0 V. Fig 5. Typical system configuration when using an external VLCD HOST PROCESSOR/ MICRO- CONTROLLER R ≤ tr 2Cb SDA SCL 60 segment drives 8 backplanes LCD PANEL (up to 480 elements) PCA9620 A0 A1 VDD1 VSS VSS 013aaa248 VLCD VLCD VDD2 VDD1 CLK n.c. |
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