PCA9620 datasheet(52/71 Pages) NXP

52 / 71 page

PCA9620

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Product data sheet

Rev. 1 — 9 December 2010

52 of 71

NXP Semiconductors

PCA9620

Universal LCD driver for low multiplex rates

The I2C-bus protocol is shown in Figure 47. The sequence is initiated with a START

condition (S) from the I2C-bus master which is followed by one of the four PCA9620 slave

addresses available. All PCA9620’s with the corresponding A1 and A0 level acknowledge

in parallel to the slave address, but all PCA9620 with the alternative A1 and A0 levels

ignore the whole I2C-bus transfer.

After acknowledgement, a control byte follows which defines if the next byte is RAM or

command information. The control byte also defines if the next byte is a control byte or

further RAM or command data.

In this way it is possible to configure the device and then fill the display RAM with little

overhead.

The display bytes are stored in the display RAM at the address specified by the data

pointer.

The acknowledgement after each byte is made only by the (A0 and A1) addressed

PCA9620. After the last display byte, the I2C-bus master issues a STOP condition (P).

Alternatively a START may be issued to RESTART an I2C-bus access.

In case that a temperature readout (byte TD[7:0]) is made the R/W bit must be logic 1 and

then the next data byte following is provided by the PCA9620 as shown in Figure 49.

Table 33.

Control byte description

Bit

Symbol

Value

Description

7CO

continue bit

last control byte

control bytes continue

6RS

command register

data register

5 to 0

not relevant

Fig 48. Control byte format

Fig 49. I2C-bus protocol read mode

mgl753

not relevant

210

MSB

LSB

013aaa294

S 0 1110

slave address

temperature

readout byte

A P

R/W = 1

acknowledge

from PCA9620

acknowledge

from master

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