PCA9620 datasheet(38/71 Pages) NXP

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PCA9620

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Product data sheet

Rev. 1 — 9 December 2010

38 of 71

NXP Semiconductors

PCA9620

Universal LCD driver for low multiplex rates

The Voffset(LCD) value can be calculated with the equations given in Table 30:

(12)

[1]

No temperature compensation is possible above 80

°C. Above this value, the system maintains the

compensation value from 80

°C.

Example: Assumed that Tamb = −8 °C; TD[7:0] = 22h; MB = −0.5:

The VT[7:0] term is calculated using the digital temperature value TD[7:0] which is

provided by the temperature measurement block (Section 7.4.7). Therefore the accuracy

of the temperature measurement block (Tacc, see Table 35 on page 55) will be directly

translated to the LCD voltage deviation

ΔV

LCD.

Since VT[7:0] = f[T,slope] and Tacc = ±6 °C then

, where slope has one

of the possible values specified in Table 29. This term will be added to the total LCD

voltage deviation

ΔV

offset(LCD)tot over the temperature range. So the total VLCD offset will

be:

7.5 Oscillator

The internal logic and LCD drive signals of the PCA9620 are timed by a frequency fclk

which either is the built-in oscillator frequency fosc or equals an external clock frequency.

7.5.1 Internal oscillator

When the internal oscillator is used, it is possible to make the clock signal available on pin

CLK by using the oscillator-ctrl command (see Table 7 on page 6). If this is not intended,

pin CLK should be left open. At power-on the signal at pin CLK is disabled and pin CLK is

in 3-state.

The duty cycle of the output clock provided on the CLK pin is not always 50 : 50. Table 17

on page 9 shows the expected duty cycle for each of the chosen frame frequencies.

7.5.2 External clock

In applications where an external clock needs to be applied to the PCA9620, bit OSC (see

Table 7 on page 6) must be set logic 1. In this case pin CLK becomes an input.

The CLK signal is a signal that is fed into the VDD1 domain so it must have an amplitude

equal to the VDD1 voltage supplied to the chip and be referenced to VSS.

The clock frequency (fclk) determines the LCD frame frequency ffr.

Table 30.

Calculation of the temperature compensated voltage VT

Temperature range

TD[7:0]

Offset equation for VT

≤ −40 °C0h

−40 °C ≤ T ≤−10 °C

0h to 20h

−10 °C < T ≤ 20 °C

21h to 40h

°C < T ≤ 50 °C

41h to 60h

°C < T < 80 °C

61h to 7Eh

°C ≤ T7Fh[1]

offset LCD

()

–

TD 7:0

[] 32

–

() MA 32 MB

–

TD 7:0

[] 64

–

()

() MB

TD 7:0

[] 64

–

() MC

TD 7:0

[] 96

–

() MD

offset LCD

()

mTD[7:0]

–

() MB

30mV

–

()

0.5

–

()

30mV

–

0.5

–

450mV

ΔV

acc

slope

ΔV

offset LCD

()tot

ΔV

LCD

ΔV

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