PCA9620 datasheet(32/71 Pages) NXP

32 / 71 page

PCA9620

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Product data sheet

Rev. 1 — 9 December 2010

32 of 71

NXP Semiconductors

PCA9620

Universal LCD driver for low multiplex rates

It has to be taken into account that the charge pump has to be configured (via bit CPC)

properly to obtain the desired voltage range. For example, if VDD2 = 3.0 V and CPC is set

to 2

× V

DD2 (logic 0) then the maximum theoretical value that the charge pump can reach

is VLCD = 6.0 V. But in reality, lower values will be reached due to internal resistances, see

Section 7.4.5. So, if the requested value for VLCD = 7.0 V then the charge pump has to be

configured with CPC set to 3

× V

DD2 (logic 1).

Programmable range of VPR[7:0] is from 0h to FFh. This would allow to achieve

VLCD > 9.0 V, but the PCA9620 has a built-in automatic limitation of VLCD at 9.0 V.

In case that VDD2 is higher than 3.0 V, then it is important that VPR[7:0] is set to a value

such that the resultant VLCD (including the temperature correction of VT[7:0]) is higher

than VDD2.

7.4.4 External VLCD supply

VLCD can be directly supplied to the VLCD pin. In this case the internal charge pump must

not be enabled otherwise a high current may occur on pin VDD2 and pin VLCD. When VLCD

is supplied externally, no internal temperature compensation occurs on this voltage even if

bit TCE is set logic 1 (see Section 7.4.8 on page 36). The VLCD voltage which is supplied

externally will be available at the segments and backplanes of the device through the

chosen bias system. Also programming the VPR[7:0] bit field has no effect on the VLCD

which is externally supplied.

(1) If VDD2 > 3.0 V then VPR[7:0] must be set so that VLCD > VDD2.

(2) Automatic limitation for VLCD > 9.0 V.

Fig 24. VLCD programming of PCA9620 (assuming VT[7:0] = 0h)

013aaa258

VLCD

VPR[7:0]

. . . . . . . . . . . . . . . . . . . . . . . .

. . .

9 V

(1)

(2)

VDD2

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