PCA9620 datasheet(56/71 Pages) NXP

56 / 71 page

PCA9620

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 1 — 9 December 2010

56 of 71

NXP Semiconductors

PCA9620

Universal LCD driver for low multiplex rates

[1]

When supplying external VLCD it must be VLCD ≥ VDD2. Also when using the internal charge pump to generate a certain VLCD, VPR[7:0]

must be set to a value that the voltage is higher than VDD2 (see Section 7.4.3 on page 31).

[2]

Calibrated at testing stage with VDD1 = VDD2 = 5.0 V. VLCD temperature compensation is disabled.

[3]

Display is disabled; I2C-bus inactive; temperature measurement disabled.

[4]

The typical value is defined at VDD1 =VDD2 = 5.0 V, VLCD = 7.0 V and 30 °C.

[5]

Temperature measurement enabled; 1:8 multiplex drive mode; 1

⁄

4 bias; display enabled; LCD outputs are open circuit; RAM is all written

with logic 1; inputs at VSS or VDD; internal clock with the default prescale factor; I2C-bus inactive.

[6]

VDD2 = 5.0 V; charge pump set to 2 × VDD2; VPR[7:0] set for VLCD = 7.0 V; 1:8 multiplex drive mode; 1⁄4 bias; temperature measurement

enabled; display enabled; LCD outputs are open circuit; RAM is all written with logic 1; inputs at VSS or VDD; external clock with 50 %

duty factor; I2C-bus inactive.

[7]

External supplied VLCD = 7.0 V; 1:8 multiplex drive mode; 1⁄4 bias; temperature measurement enabled; display enabled; LCD outputs

are open circuit; RAM is all written with logic 1; inputs at VSS or VDD; external clock with 50 % duty factor; I2C-bus inactive.

[8]

VDD2 = 5.0 V; charge pump set to 2 × VDD2; VPR[7:0] set for VLCD = 9.0 V; display disabled; CPF (see Table 22 on page 11) set logic 0.

[9]

VDD2 = 4.0 V; charge pump set to 3 × VDD2; VPR[7:0] set for VLCD = 9.0 V; display disabled; CPF (see Table 22 on page 11) set logic 0.

[10] If VDD1 > VPOR then no reset occurs.

[11] In case of an ESD event, the value may increase slightly.

[12] Variation between any 2 backplanes on a given voltage level; static measured.

[13] Variation between any 2 segments on a given voltage level; static measured.

[14] Outputs measured one at a time.

I2C-bus; pins SDA and SCL

input voltage

VSS − 0.5 -

5.5

VIL

LOW-level input voltage

pins SCL, SDA

0.3VDD

VIH

HIGH-level input voltage

pins SCL, SDA

0.7VDD

output voltage

pins SCL, SDA

−0.5

5.5

IOL

LOW-level output current

VOL = 0.4 V; VDD = 5 V; on pin SDA

leakage current

VI =VDD or VSS

[11] -0

μA

LCD outputs

ΔV

output voltage variation

on pins BP0 to BP7

[12]

−15

+15

on pins S0 to S59

[13]

−15

+15

output resistance

VLCD = 7 V; on pins BP0 to BP7

[14] 0.3

0.8

1.5

VLCD = 7 V; on pins S0 to S59

[14] 0.6

1.5

Table 35.

Static characteristics …continued

VDD1 = 2.5 V to 5.5 V; VDD2 = 2.5 V to 5.5 V; VSS = 0 V; VLCD = 2.5 V to 9.0 V; Tamb = −40 °C to +105 °C; unless otherwise

specified.

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

PCA9620 датащи(PDF) 56 Page - NXP Semiconductors

PCA9620 датащи(HTML) 56 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71

датащи скачать

ссылки URL