PCA9620 datasheet(43/71 Pages) NXP

43 / 71 page

PCA9620

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 1 — 9 December 2010

43 of 71

NXP Semiconductors

PCA9620

Universal LCD driver for low multiplex rates

7.9.1.2

RAM filling in 1:2 multiplex drive mode

In the 1:2 multiplex drive mode the eight transmitted data bits are placed in four

successive display RAM columns of two rows (see Figure 33).

In order to fill the whole two RAM rows 15 bytes need to be sent to the PCA9620. After the

last byte sent the data pointer is wrapped around to column 0 to start a possible RAM

content update (see Figure 34). Even if a data byte is transmitted during the wrapping of

the data pointer, then all the bits in the byte will be written correctly.

7.9.1.3

RAM filling in 1:4 multiplex drive mode

In the 1:4 multiplex drive mode the eight transmitted data bits are placed in two

successive display RAM columns of four rows (see Figure 35).

Fig 32. Discarded bits and data pointer wrap around at the end of data transmission

01234567

48 49 50 51 52

display RAM

data pointer

53 54 55 56 57 58 59

a7 a6 a5 a4 a3 a2 a1 a0

f7 f6 f5 f4 f3 f2 f1 f0 g7 g6 g5 g4 g3 g2 g1 g0

discarded

wrap around

013aaa287

Fig 33. Display RAM filling order in 1:2 multiplex drive mode

Fig 34. Data pointer wrap around in 1:2 multiplex drive mode

55 56 57 58 59

LSB

MSB

transmitted data byte

013aaa264

display RAM columns/segment outputs (S)

columns

display RAM rows/

backplane outputs

(BP)

rows

55 56 57 58 59

display RAM

data pointer

wrap around

013aaa288

PCA9620 датащи(PDF) 43 Page - NXP Semiconductors

PCA9620 датащи(HTML) 43 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71

датащи скачать

ссылки URL