PCA9620 datasheet(20/71 Pages) NXP

20 / 71 page

PCA9620

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Product data sheet

Rev. 1 — 9 December 2010

20 of 71

NXP Semiconductors

PCA9620

Universal LCD driver for low multiplex rates

Remark: It is necessary to run the power-down sequence before removing the supplies.

Depending on the application, care must be taken that no other signals are present at the

chip input or output pins when removing the supplies (please refer to Section 9 on

page 53). Otherwise this may cause unwanted display artifacts. In case of uncontrolled

removal of supply voltages the PCA9620 will not be damaged.

Remark: Static voltages across the liquid crystal display can build up when the external

LCD supply voltage (VLCD) is on while the IC supply voltage (VDD1 or VDD2) is off, or vice

versa. This may cause unwanted display artifacts. To avoid such artifacts, external VLCD,

VDD1, and VDD2 must be applied or removed together.

Remark: A clock signal must always be supplied to the device when the device is active;

removing the clock may freeze the LCD in a DC state, which is not suitable for the liquid

crystal. It is recommended to first disable the display and afterwards to remove the clock

signal.

7.4 LCD voltage

7.4.1 LCD voltage selector

The LCD voltage selector co-ordinates the multiplexing of the LCD in accordance with the

selected LCD drive configuration. The operation of the voltage selector is controlled by the

set-bias-mode command (see Table 14 on page 8) and the set-MUX-mode command

(see Table 13 on page 8).

Intermediate LCD biasing voltages are obtained from an internal voltage divider. The

biasing configurations that apply to the preferred modes of operation, together with the

biasing characteristics as functions of VLCD and the resulting discrimination ratios (D), are

given in Table 26.

Discrimination is a term which is defined as the ratio of the on and off RMS voltage across

a segment. It can be thought of as a measurement of contrast.

Fig 13. Recommended power-down sequence when using an external supplied VLCD and

an external clock signal

START

Disable dis-

play by setting

bit E logic 0

Disable tem-

perature mea-

surement by

setting bit

TME logic 0

013aaa256

STOP

Bring pin CLK

to 3-state by

setting bit

OSC and bit

COE logic 0

External

clock may

be switched

off

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