 |
поискавой системы для электроныых деталей |
|
|
поискавой системы для электроныых деталей |
|
PCA9620 датащи(PDF) 59 Page - NXP Semiconductors |
|
|
|||||||||||||||||||||||||||||
PCA9620 датащи(HTML) 59 Page - NXP Semiconductors |
|
|
59 / 71 page  PCA9620 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 1 — 9 December 2010 59 of 71 NXP Semiconductors PCA9620 Universal LCD driver for low multiplex rates 12. Dynamic characteristics [1] Internal calibration made with OTP so that the maximum variation is ±15 % over whole temperature and voltage range. The typical f osc generates a typical frame frequency of 200 Hz when the default frequency division factor is used (see Section 7.5.3 on page 39). [2] The typical value is defined at VDD1 =VDD2 = 5.0 V and 30 °C. [3] All timing values are valid within the operating supply voltage and ambient temperature range and are referenced to VIL and VIH with an input voltage swing of VSS to VDD. [4] tVD;DAT = minimum time for valid SDA output following SCL LOW. [5] tVD;ACK = time for acknowledgement signal from SCL LOW to SDA output LOW. Table 36. Dynamic characteristics VDD1 = 2.5 V to 5.5 V; VDD2 = 2.5 V to 5.5 V; VSS = 0 V; VLCD = 2.5 V to 9.0 V; Tamb = −40 °C to +105 °C; unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit fosc oscillator frequency on pin CLK; see Table 17 on page 9 [1][2] 8160 9600 11040 Hz fclk(ext) external clock frequency 450 - 14500 Hz tclk(H) HIGH-level clock time external clock source used 33 - - μs tclk(L) LOW-level clock time 33 - - μs Timing characteristics: I2C-bus[3] fSCL SCL frequency - - 400 kHz tBUF bus free time between a STOP and START condition 1.3 - - μs tHD;STA hold time (repeated) START condition 0.6 - - μs tSU;STA set-up time for a repeated START condition 0.6 - - μs tVD;DAT data valid time [4] --0.9 μs tVD;ACK data valid acknowledge time [5] --0.9 μs tLOW LOW period of the SCL clock 1.3 - - μs tHIGH HIGH period of the SCL clock 0.6 - - μs tf fall time of both SDA and SCL signals - - 0.3 μs tr rise time of both SDA and SCL signals - - 0.3 μs Cb capacitive load for each bus line - - 400 pF tSU;DAT data set-up time 100 - - ns tHD;DAT data hold time 0 - - ns tSU;STO set-up time for STOP condition 0.6 - - μs tw(spike) spike pulse width - - 50 ns |
|
ссылки URL |
| Вашему бизинису помогли Аллдатащит? [ DONATE ] |
Что такое Аллдатащит | реклама | контакт | Конфиденциальность | Ссылка на техническое описание | обмен ссыками | поиск по производителю All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
Russian ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
