PCA9620 datasheet(42/71 Pages) NXP

42 / 71 page

PCA9620

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Product data sheet

Rev. 1 — 9 December 2010

42 of 71

NXP Semiconductors

PCA9620

Universal LCD driver for low multiplex rates

The data pointer is automatically incremented in accordance with the chosen LCD

multiplex drive mode configuration. That is, after each byte is stored, the contents of the

data pointer are incremented

• by eight (static drive mode)

• by four (1:2 multiplex drive mode)

• by two (1:4 multiplex drive mode)

• by one or two (1:6 multiplex drive mode), see Figure 37 on page 45

• by one (1:8 multiplex drive mode)

If the data pointer reaches the end of the RAM row it is automatically wrapped around to

address 0. This means that it can be continuously written to or read from the display RAM.

The data pointer should always be set to an address where the remaining RAM is divisible

by eight because odd bits will be discarded (see Figure 32). This behavior is actually only

shown in static drive mode because of the fact that the 60 RAM cells can’t be divided by

eight without remainder.

If an I2C-bus data access is terminated early then the state of the data pointer is unknown.

The data pointer must then be re-written prior to further RAM accesses.

7.9.1.1

RAM filling in static drive mode

In the static drive mode the eight transmitted data bits are placed in eight successive

display RAM columns in row 0 (see Figure 31).

In order to fill the whole RAM row, 8 bytes must be sent to the PCA9620, but the last 4 bits

from the last byte are discarded, and the data pointer is wrapped around to column 0 to

start a possible RAM content update (see Figure 32).

Fig 31. Display RAM filling order in static drive mode

55 56 57 58 59

MSB

LSB

transmitted data byte

display RAM columns/segment outputs (S)

columns

display RAM rows/

backplane outputs

(BP)

rows

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