910GL datasheet(204/426 Pages) INTEL

204 / 426 page

Device 2 Function 1 (D2:F1) Configuration Registers

(Intel® 82915G/82915GV/82915GL/ 82910GL Only)

204

Datasheet

10.2

Device 2 – PCI I/O Registers

The following are not PCI configurations registers; they are I/O registers.

10.2.1

MMIO_INDEX—MMIO Address Register

I/O Address:

IOBAR + 0h

Size:

32 bits

MMIO_INDEX: A 32 bit I/O write to this port loads the offset of the memory-mapped I/O

(MMIO) register that needs to be accessed. An I/O Read returns the current value of this register.

An 8/16-bit I/O write to this register is completed by the GMCH but does not update this register.

This mechanism to access internal graphics MMIO registers must not be used to access VGA I/O

registers that are mapped through the MMIO space. VGA registers must be accessed directly

through the dedicated VGA IO ports.

Bit

Access &

Default

Description

31:2

R/W

00000000 h

MMIO register space of Device 2.

1:0

Reserved

10.2.2

MMIO_DATA—MMIO Data Register

I/O Address:

IOBAR + 4h

Size:

32 bits

MMIO_DATA: A 32 bit I/O write to this port is re-directed to the MMIO register pointed to by

the MMIO-index register. A 32 bit I/O read to this port is re-directed to the MMIO register

pointed to by the MMIO-index register. 8 or 16 bit I/O writes are completed by the GMCH and

may have un-intended side effects; hence, they must not be used to access the data port. 8 or 16

bit I/O reads are completed normally.

Bit

Access &

Default

Description

31:0

R/W

00000000 h

MMIO Data Window

910GL датащи(PDF) 204 Page - Intel Corporation

910GL датащи(HTML) 204 Page - Intel Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

датащи скачать

ссылки URL