910GL datasheet(191/426 Pages) INTEL

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Integrated Graphics Device Registers (D2:F0)

(Intel® 82915G/82915GV/82915GL/ 82910GL GMCH Only)

Datasheet

191

9.1.31

SWSMI—Software SMI (D2:F0)

PCI Device:

Address Offset:

E0h

Default Value:

0000h

Access:

R/W

Size:

16 bits

As long as there is the potential that DVO port legacy drivers exist that expect this register at this

address, Dev2, F0, address E0h–E1h must be reserved for this register.

Bit

Access &

Default

Description

15:8

R/W

00h

SW scratch bits

7:1

R/W

00h

Software Flag: This field is used to indicate caller and SMI function desired, as

well as return result.

R/W

GMCH Software SMI Event: When Set, this bit will trigger an SMI. Software

must write a 0 to clear this bit

9.1.32

ASLE—System Display Event Register (D2:F0)

PCI Device:

Address Offset:

E4h

Default Value:

00000000h

Access:

R/W

Size:

32 bits

Byte, Word, or Double Word PCI configuration cycles can access this register.

Bit

Access &

Default

Description

31:8

R/W

00h

ASLE Scratch Trigger 3: When written, this scratch byte triggers an interrupt

when IER bit 0 is enabled and IMR bit 0 is unmasked. If written as part of a 16-

bit or 32-bit write, only one interrupt is generated in common.

23:16

R/W

00h

ASLE Scratch Trigger 2: When written, this scratch byte triggers an interrupt

when IER bit 0 is enabled and IMR bit 0 is unmasked. If written as part of a 16-

bit or 32-bit write, only one interrupt is generated in common.

15:8

R/W

00h

ASLE Scratch Trigger 1: When written, this scratch byte triggers an interrupt

when IER bit 0 is enabled and IMR bit 0 is unmasked. If written as part of a 16-

bit or 32-bit write, only one interrupt is generated in common.

7:0

R/W

00h

ASLE Scratch Trigger 0: When written, this scratch byte triggers an interrupt

when IER bit 0 is enabled and IMR bit 0 is unmasked. If written as part of a 16-

bit or 32-bit write, only one interrupt is generated in common.

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