910GL datasheet(170/426 Pages) INTEL

170 / 426 page

Host-PCI Express* Bridge Registers (D1:F0)

(Intel® 82915G/82915P/82915PL Only)

170

Datasheet

8.1.57

LE1D—Link Entry 1 Description (D1:F0)

PCI Device:

Address Offset:

150h

Default Value:

00000000h

Access:

RO, R/WO

Size:

32 bits

This register provides the First part of a Link Entry that declares an internal link to another Root

Complex Element.

Bit

Access &

Default

Description

31:24

00h

Target Port Number: This field specifies the port number associated with the

element targeted by this link entry (Egress Port). The target port number is with

respect to the component that contains this element as specified by the target

component ID.

23:16

R/WO

00h

Target Component ID: This field indicates the physical or logical component that

is targeted by this link entry. A value of 0 is reserved; Component IDs start at 1.

This value is a mirror of the value in the Component ID field of all elements in this

component. The value only needs to be written in one of the mirrored fields and it

will be reflected everywhere that it is mirrored.

15:2

Reserved

Link Type: This field indicates that the link points to memory-mapped space (for

RCRB). The link address specifies the 64-bit base address of the target RCRB.

R/WO

Link Valid:

0 = Link Entry is not valid and will be ignored.

1 = Link Entry specifies a valid link.

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