910GL datasheet(150/426 Pages) INTEL

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Host-PCI Express* Bridge Registers (D1:F0)

(Intel® 82915G/82915P/82915PL Only)

150

Datasheet

8.1.31

PEG_CAPL—PCI Express* Capability List (D1:F0)

PCI Device:

Address Offset:

A0h

Default Value:

0010h

Access:

Size:

16 bits

This register enumerates the PCI Express capability structure.

Bit

Access &

Default

Description

15:8

00h

Pointer to Next Capability: This value terminates the capabilities list. The Virtual

Channel capability and any other PCI Express* specific capabilities that are

reported via this mechanism are in a separate capabilities list located entirely

within PCI Express extended configuration space.

7:0

10h

Capability ID: This field identifies this linked list item (capability structure) as

being for PCI Express registers.

8.1.32

PEG_CAP—PCI Express*-G Capabilities (D1:F0)

PCI Device:

Address Offset:

A2h

Default Value:

0141h

Access:

Size:

16 bits

Indicates PCI Express device capabilities.

Bit

Access &

Default

Description

15:14

Reserved

13:9

00h

Interrupt Message Number: Hardwired to 0.

R/WO

Slot Implemented

0 = The PCI Express* Link associated with this port is connected to an integrated

component or is disabled.

1 = The PCI Express Link associated with this port is connected to a slot.

BIOS must initialize this field appropriately if a slot connection is not implemented.

7:4

Device/Port Type: Hardwired to 0100 to indicate root port of PCI Express Root

Complex.

3:0

PCI Express Capability Version: Hardwired to 1 as it is the first version.

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