910GL datasheet(148/426 Pages) INTEL

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Host-PCI Express* Bridge Registers (D1:F0)

(Intel® 82915G/82915P/82915PL Only)

148

Datasheet

8.1.28

MC—Message Control (D1:F0)

PCI Device:

Address Offset:

92h

Default Value:

0000h

Access:

RO, R/W

Size:

16 bits

System software can modify bits in this register, but the device is prohibited from doing so.

If the device writes the same message multiple times, only one of those messages is guaranteed to

be serviced. If all of them must be serviced, the device must not generate the same message again

until the driver services the earlier one.

Bit

Access &

Default

Description

15:8

Reserved

64-bit Address Capable: Hardwired to 0 to indicate that the function does not

implement the upper 32 bits of the Message Address register and is incapable of

generating a 64-bit memory address.

6:4

R/W

000b

Multiple Message Enable (MME): System software programs this field to

indicate the actual number of messages allocated to this device. This number will

be equal to or less than the number actually requested.

000 = 1 message allocated

001–111 = Reserved

3:1

000b

Multiple Message Capable (MMC): System software reads this field to

determine the number of messages being requested by this device.

000 = 1 message requested

001–111 = Reserved

R/W

MSI Enable (MSIEN) Controls the ability of this device to generate MSIs.

0 = MSI will not be generated.

1 = MSI will be generated when we receive PME or HotPlug messages. INTA will

not be generated and INTA Status (PCISTS1[3]) will not be set.

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