910GL datasheet(122/426 Pages) INTEL

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DMIBAR Registers—Direct Media Interface (DMI) RCRB

122

Datasheet

7.1.11

DMILCAP—DMI Link Capabilities

MMIO Range:

DMIBAR

Address Offset:

084h

Default Value:

00012C41h

Access:

R/WO, RO

Size:

32 bits

This register indicates DMI specific capabilities.

Bit

Access &

Default

Description

31:18

Reserved

17:15

R/WO

010b

L1 Exit Latency (EL1). L1 not supported on DMI.

14:12

R/WO

010b

L0s Exit Latency (EL0): This field indicates that exit latency is 128 ns to less

than 256 ns.

11:10

11b

Active State Link PM Support (APMS): This field indicates that L0s is supported

on DMI.

9:4

Maximum Link Width (MLW): This field indicates the maximum link width is

4 ports.

3:0

Maximum Link Speed (MLS): This field indicates the link speed is 2.5 Gb/s.

7.1.12

DMILCTL—DMI Link Control

MMIO Range:

DMIBAR

Address Offset:

088h

Default Value:

0000h

Access:

R/W

Size:

16 bits

This register allows control of DMI.

Bit

Access &

Default

Description

15:8

Reserved

R/W

Extended Synch (ES):

1 = Forces extended transmission of FTS ordered sets when exiting L0s prior to

entering L0 and extra TS1 sequences at exit from L1 prior to entering L0.

6:2

Reserved

1:0

R/W

00b

Active State Link PM Control (APMC): Indicates whether DMI should enter L0s.

00 = Disabled

01 = L0s entry enabled

10 = Reserved

11 = Reserved

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