ADS58C48IPFPR datasheet(27/70 Pages) TI

27 / 70 page

ADS58C48

www.ti.com

SLAS689 – MAY 2010

NUMBER

PIN NAME

DESCRIPTION

OF PINS

TYPE

NUMBER

INA_P,

Differential analog input, Channel A

23, 24

INA_M

INB_P,

Differential analog input, Channel B

26, 27

INB_M

INC_P,

Differential analog input, Channel C

34, 35

INC_M

IND_P,

Differential analog input, Channel D

37, 38

IND_M

Outputs the common-mode voltage (0.95 V) that can be used externally to bias

the analog input pins.

RESET

Serial interface RESET input.

The user must initialize internal registers through hardware RESET by applying a

high-going pulse on this pin or by using software reset option. Refer to SERIAL

INTERFACE section. The pin has an internal 100k

Ω pull-down resistor.

SCLK

Serial interface clock input. The pin has an internal 100-k

Ω pull-down resistor.

SDATA

Serial interface data input. The pin has an internal 100-k

Ω pull-down resistor.

SEN

Serial interface enable input. The pin has an internal 100-k

Ω pull-up resistor to

DRVDD

SDOUT

This pin functions as serial interface register readout, when the <READOUT> bit

is enabled.

When <READOUT> = 0, this pin is put in high impedance state.It is a CMOS

output pin running off DRVDD supply.

PDN

Power down control pin. The pin has an internal 150-k

Ω pull-down resistor to

DRGND.

SNRB_1,

SNRBoost 3G control pins. Each pin has an internal 150-k

Ω pull-down resistor to

41, 40

SNRB_2

DRGND.

DRVDD

1.8 V, digital supply

1, 60, 69, 70

CLKOUTP,

Differential output clock

68, 67

CLKOUTM

CHA<0>_P,

Differential output data pair, '0' and D0 multiplexed – Channel A

5,4 Refer to

CHA<0>_M

Figure 9

CHA<2>_P,

Differential output data D1 and D2 multiplexed, true – Channel A

7,6

CHA<2>_M

CHA<4>_P,

Differential output data D3 and D4 multiplexed, true – Channel A

9,8

CHA<4>_M

CHA<6>_P,

Differential output data D5 and D6 multiplexed, true – Channel A

11,10

CHA<6>_M

CHA<8>_P,

Differential output data D7 and D8 multiplexed, true – Channel A

13,12

CHA<8>_M

CHA<10>_P,

Differential output data D9 and D10 multiplexed, true – Channel A

15,14

CHA<10>_M

CHB<0>_P,

Differential output data pair, '0' and D0 multiplexed – Channel B

72,71

CHB<0>_M

CHB<2>_P,

Differential output data D1 and D2 multiplexed, true – Channel B

74,73

CHB<2>_M

CHB<4>_P,

Differential output data D3 and D4 multiplexed, true – Channel B

76,75

CHB<4>_M

CHB<6>_P,

Differential output data D5 and D6 multiplexed, true – Channel B

78,77

CHB<6>_M

CHB<8>_P,

Differential output data D7 and D8 multiplexed, true – Channel B

80,79

CHB<8>_M

CHB<10>_P,

Differential output data D9 and D10 multiplexed, true – Channel B

3,2

CHB<10>_M

CHC<0>_P,

Differential output data pair, '0' and D0 multiplexed – Channel C

55,54

CHC<0>_M

Submit Documentation Feedback

Product Folder Link(s) :ADS58C48

ADS58C48IPFPR датащи(PDF) 27 Page - Texas Instruments

ADS58C48IPFPR датащи(HTML) 27 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70

датащи скачать

ссылки URL