ADS58C48IPFPR datasheet(7/70 Pages) TI

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Dn_Dn+1_P

DAP/DBP

Dn_Dn+1_M

DAM/DBM

GND

* With external 100-

termination

OCM

Logic 0

ODL

Logic 1

ODH

T0334-03

ADS58C48

www.ti.com

SLAS689 – MAY 2010

DIGITAL CHARACTERISTICS

The DC specifications refer to the condition where the digital outputs are not switching, but are permanently at a valid logic

level 0 or 1. AVDD = 1.8 V, DRVDD = 1.8 V

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

DIGITAL INPUTS – RESET, SCLK, SDATA, SEN, SNRB_1, SNRB_2 and PDN

High-level input voltage

RESET, SCLK, SDATA and SEN support

1.3

1.8 V and 3.3 V CMOS logic levels.

Low-level input voltage

0.4

High-level input

SDATA, SCLK(1)

VHIGH = 1.8 V

µA

current

SEN(2)

VHIGH = 1.8 V

µA

Low-level input

SDATA, SCLK

VLOW = 0 V

µA

current

SEN

VLOW = 0 V

–10

µA

DIGITAL OUTPUTS – CMOS INTERFACE (CHx_Dn, SDOUT)

High-level output voltage

DRVDD – 0.1

DRVDD

Low-level output voltage

0.1

DIGITAL OUTPUTS – LVDS INTERFACE (CHx<>P/M, CLKOUTP/M)

VODH, High-level output voltage

(3)

Standard swing LVDS

275

350

425

VODL, Low-level output voltage

(3)

Standard swing LVDS

–425

–350

–275

VODH, High-level output voltage

(3)

Low swing LVDS(4)

200

VODL, Low-level output voltage

(3)

Low swing LVDS(4)

–200

VOCM, Output common-mode voltage

0.9

1.05

1.25

(1)

SDATA, SCLK have internal 170-k

Ω pull-down resistor.

(2)

SEN has internal 170-k

Ω pull-up resistor to AVDD.

(3)

With external 100-

Ω termination.

(4)

See the LVDS Output Data and Clock Buffers section in the Application Information.

Figure 2. LVDS Output Voltage Levels

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