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ADS58C48IPFPR датащи(PDF) 1 Page - Texas Instruments |
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ADS58C48IPFPR датащи(HTML) 1 Page - Texas Instruments |
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1 / 70 page ![]() ADS58C48 www.ti.com SLAS689 – MAY 2010 Quad Channel IF Receiver with SNRBoost 3G Check for Samples: ADS58C48 1 FEATURES DESCRIPTION • Maximum Sample Rate: 200 MSPS The ADS58C48 is a quad channel 11-bit A/D converter with sampling rate up to 200 MSPS. It uses • High Dynamic Performance innovative design techniques to achieve high dynamic – SFDR 82 dBc at 140 MHz performance, while consuming extremely low power – 72.3 dBFS SNR in 60 MHz BW Using at 1.8V supply. This makes it well-suited for SNRBoost 3G technology multi-carrier, wide band-width communications applications. • SNRBoost 3G Highlights – Supports Wide Bandwidth up to 60 MHz The ADS58C48 uses third-generation SNRBoost 3G technology to overcome SNR limitation due to – Programmable Bandwidths – 60 MHz, 40 quantization noise (for bandwidths < Nyquist, Fs/2). MHz, 30 MHz, 20 MHz Enhancements in the SNRBoost 3G technology allow – Flat Noise Floor within the Band support for SNR improvements over wide bandwidths – Independent SNRBoost 3G Coefficients for (up to 60 MHz). In addition, separate SNRBoost 3G Every Channel coefficients can be programmed for each channel. • Output Interface The device has digital gain function that can be used to improve SFDR performance at lower full-scale – Double Data Rate (DDR) LVDS with input ranges. It includes a dc offset correction loop Programmable Swing and Strength that can be used to cancel the ADC offset. – Standard Swing: 350 mV The digital outputs of all channels are output as DDR – Low Swing: 200 mV LVDS (Double Data Rate) together with an LVDS – Default Strength: 100- Ω Termination clock output. The low data rate of this interface (400 – 2x Strength: 50- Ω Termination Mbps at 200 MSPS sample rate) makes it possible to use low-cost FPGA-based receivers. The strength of – 1.8V Parallel CMOS Interface Also the LVDS output buffers can be increased to support Supported 50- Ω differential termination. This allows the output • Ultra-Low Power with Single 1.8-V Supply clock signal to be connected to two separate receiver – 0.9-W Total Power chips with an effective 50- Ω termination (such as the two clock ports of the GC5330). – 1.32-W Total Power (200 MSPS) with SNRBoost 3G on all 4 Channels The same digital output pins can also be configured – 1.12-W Total Power (200 MSPS) with as a parallel 1.8-V CMOS interface. SNRBoost 3G on 2 Channels It includes internal references while the traditional • Programmable Gain up to 6dB for SNR/SFDR reference pins and associated decoupling capacitors Trade-Off have been eliminated. The device is specified over the industrial temperature range (–40°C to 85°C). • DC Offset Correction • Supports Low Input Clock Amplitude • 80-TQFP Package 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Copyright © 2010, Texas Instruments Incorporated Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. |
Аналогичный номер детали - ADS58C48IPFPR |
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Аналогичное описание - ADS58C48IPFPR |
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