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ADS58C48IPFPR датащи(PDF) 41 Page - Texas Instruments

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номер детали ADS58C48IPFPR
подробное описание детали  Quad Channel IF Receiver with SNRBoost 3G
PDF  70 Pages
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производитель  TI [Texas Instruments]
домашняя страница  http://www.ti.com
Logo TI - Texas Instruments

ADS58C48IPFPR датащи(HTML) 41 Page - Texas Instruments

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THD
Input Clock Duty Cycle (%)
SNR
Fin = 20MHz
0.1
0.15
0.2
0.25
0.3
0.35
0.4
0.45
0.5
0.55
0
20
40
60
80
100
120
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200
Sampling Frequency (MSPS)
AVDD = 1.8V
Fin = 2.5MHz
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
0
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Sampling Frequency (MSPS)
Default after Reset
Digital Gain + Offset-Correction Enable
SNR Boost ON for 2ch’s (60MHz Filter)
SNR Boost ON for 4ch’s (60MHz Filter)
SNR Boost ON for 4ch’s + Digital Gain
+ Offset Correction
ADS58C48
www.ti.com
SLAS689 – MAY 2010
TYPICAL CHARACTERISTICS (continued)
All plots are at 25°C, AVDD = 1.8 V, DRVDD = 1.8 V, maximum rated sampling frequency, sine wave input clock. 1.5 VPP
differential clock amplitude, 50% clock duty cycle, –1 dBFS differential analog input, High Perf Mode disabled, 0 dB gain,
DDR LVDS output interface, 32k point FFT (unless otherwise noted)
PERFORMANCE ACROSS INPUT CLOCK DUTY CYCLE
Figure 40.
ANALOG POWER
DIGITAL POWER
vs
vs
SAMPLING FREQUENCY
SAMPLING FREQUENCY
Figure 41.
Figure 42.
Copyright © 2010, Texas Instruments Incorporated
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Product Folder Link(s) :ADS58C48



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