ADS58C48IPFPR datasheet(49/70 Pages) TI

49 / 70 page

CLKP

5 kW

VCM

5 kW

2 pF

20 W

CLKM

Clock Buffer

Ceq

1 to 3 pF, Equivalent Input Capacitance of Clock Buffer

Lpkg

4 nH

Lpkg

4 nH

Cbond

1 pF

Cbond

1 pF

Resr

100

Resr

100

S0275-04

ADS58C48

www.ti.com

SLAS689 – MAY 2010

INPUT COMMON-MODE

To ensure a low-noise, common-mode reference, the VCM pin is filtered with a 0.1-mF low-inductance capacitor

connected to ground. The VCM pin is designed to directly bias the ADC inputs (refer to Figure 54 to Figure 56).

Each ADC input pin sinks a common-mode current of approximately 0.8 mA per MSPS of clock frequency.

When a differential amplifier is used to drive the ADC (with dc-coupling), ensure that the output common-mode of

the amplifier is within the acceptable input common-mode range of the ADC inputs (Vcm ± 50mV).

CLOCK INPUT

The clock inputs of ADS58C48 can be driven differentially (sine, LVPECL or LVDS) or single-ended (LVCMOS),

with little or no difference in performance between them. The common-mode voltage of the clock inputs is set to

VCM using internal 5-k

Ω resistors. This allows using transformer-coupled drive circuits for sine wave clock or

ac-coupling for LVPECL, LVDS clock sources

Figure 57. Internal Clock Buffer

Single-ended CMOS clock can be ac-coupled to the CLKP input, with CLKM connected to ground with a 0.1-µF

capacitor, as shown in Figure 59. For best performance, the clock inputs have to be driven differentially, reducing

susceptibility to common-mode noise. For high input frequency sampling, it is recommended to use a clock

source with very low jitter. Band-pass filtering of the clock source can help reduce the effect of jitter. There is no

change in performance with a non-50% duty cycle clock input.

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