ADS58C48IPFPR datasheet(46/70 Pages) TI

46 / 70 page

Resr

200 W

10 W

Sampling

Capacitor

Csamp

2 pF

INP

INM

Cbond

1 pF

100 W

Cpar1

0.25 pF

Ron

15 W

Cpar2

1.0 pF

Ron

15 W

Ron

15 W

Cpar2

1.0 pF

100 W

3 pF

Lpkg

4 nH

Lpkg

4 nH

Cbond

1 pF

Resr

200 W

Csamp

2 pF

Sampling

Capacitor

Sampling

Switch

Sampling

Switch

RCR Filter

S0322-04

ADS58C48

SLAS689 – MAY 2010

www.ti.com

APPLICATION INFORMATION

THEORY OF OPERATION

ADS58C48 is a quad channel 11-bit A/D converter with sampling rates up to 200 MSPS.

At every rising edge of the input clock, the analog input signal of each channel is sampled simultaneously. The

sampled signal in each channel is converted by a pipeline of low resolution stages. In each stage, the sampled

and held signal is converted by a high speed, low resolution flash sub-ADC. The difference (residue) between the

stage input and its quantized equivalent is gained and propagates to the next stage. At every clock, each

succeeding stage resolves the sampled input with greater accuracy. The digital outputs from all stages are

combined in a digital correction logic block and processed digitally to create the final code, after a data latency of

10 clock cycles.

The digital output is available as either DDR LVDS or parallel CMOS and coded in either straight offset binary or

binary 2s complement format.

ANALOG INPUT

The analog input consists of a switched-capacitor based differential sample and hold architecture. This

differential topology results in very good AC performance even for high input frequencies at high sampling rates.

The INP and INM pins have to be externally biased around a common-mode voltage of 0.95 V, available on VCM

pin. For a full-scale differential input, each input pin INP, INM has to swing symmetrically between VCM + 0.5 V

and VCM – 0.5 V, resulting in a 2-Vpp differential input swing.

The input sampling circuit has a high 3-dB bandwidth that extends up to 550 MHz (measured from the input pins

to the sampled voltage).

Figure 51. Analog Input Circuit

Drive Circuit Requirements

For optimum performance, the analog inputs must be driven differentially. This improves the common-mode

noise immunity and even order harmonic rejection. A 5-

Ω to 15-Ω resistor in series with each input pin is

recommended to damp out ringing caused by package parasitic.

SFDR performance can be limited due to several reasons - the effect of sampling glitches (described below),

non-linearity of the sampling circuit and non-linearity of the quantizer that follows the sampling circuit.

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