ADS58C48IPFPR datasheet(61/70 Pages) TI

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CHx_D0

CHx_D1

CHx_D2

ADS58C48

CHx_D9

CHx_D10

CLKOUT

11Bit ADCData

D0_in

D1_in

D12_in

D13_in

D2_in

Flip-flops

Receiver(FPGA, ASICetc)

Clock_in

Useshorttracesbetween ADCoutput

andreceiverpins(1to2inches)

Useexternalclockbuffer

(>150MSPS)

Inputclock

ADS58C48

www.ti.com

SLAS689 – MAY 2010

Figure 65. Data Capture with CMOS Interface

CMOS Interface Power Dissipation

With CMOS outputs, the DRVDD current scales with the sampling frequency and the load capacitance on every

output pin. The maximum DRVDD current occurs when each output bit toggles between 0 and 1 every clock

cycle. In actual applications, this condition is unlikely to occur. The actual DRVDD current would be determined

by the average number of output bits switching, which is a function of the sampling frequency and the nature of

the analog input signal.

Digital current due to CMOS output switching = CL x DRVDD x (N x FAVG),

where CL = load capacitance, N x FAVG = average number of output bits switching.

Output Data Format

Two output data formats are supported – 2s complement and offset binary. They can be selected using the serial

interface register bit <DATA FORMAT CHx>.

In the event of an input voltage overdrive, the digital outputs go to the appropriate full scale level. For a positive

overdrive, the output code is 0x7FF in offset binary output format, and 0x3FF in 2s complement output format.

For a negative input overdrive, the output code is 0x0000 in offset binary output format and 0x400 in 2s

complement output format.

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