ADS58C48IPFPR datasheet(23/70 Pages) TI

23 / 70 page

ADS58C48

www.ti.com

SLAS689 – MAY 2010

Refer to section SNR ENHANCEMENT USING SNRBOOST

D2-D1

<PDN OBUF CMOS>(1)

CMOS data buffers enabled for all channels

CMOS data buffers powered down and output 3-stated for channel A and channel D

CMOS data buffers powered down and output 3-stated for channel B and channel C

CMOS data buffers powered down and output 3-stated for all channels

1. With CMOS interface, to power down the output clock CLKOUT, set the bits <PDN OBUF LVDS>

= 11

ADDRS

DEFAULT

A7-A0 IN

VALUE

HEX

AFTER

RESET

<DIGITAL

MODE 2>

<OVERRID

E SNRB

pins>

Refer to section SNR ENHANCEMENT USING SNRBOOST

D1-D0

<EN LVDS SWING>Enable LVDS swing control using the <LVDS SWING> bits

LVDS swing control using LVDS SWING register bits is disabled

01, 10

Do not use

LVDS swing control using LVDS SWING register bits is enabled

ADDRS

DEFAULT

A7-A0 IN

VALUE

HEX

AFTER

RESET

<STBY>

<LVDS

<LVDS DATA

<PDN

<CONFIG

CLKOUT

STRENGTH>

GLOBAL>

PDN Pin>

STRENGTH>

PDN pin functions as STBY control pin.

PDN pin functions as Global Power down control pin.

Normal operation

Total power down – All channel ADCs, internal references and output buffers are powered down.

Wake-up time from this mode is slow, typically, 100 µsec.

All LVDS data buffers have default strength to be used with 100-

Ω external termination

All LVDS data buffers have double strength to be used with 50-

Ω external termination

LVDS output clock buffer has default strength to be used with 100-

Ω external termination

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