ADS58C48IPFPR datasheet(47/70 Pages) TI

47 / 70 page

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ADS58C48

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SLAS689 – MAY 2010

Depending on the input frequency, sample rate AND input amplitude, one of these plays a dominant part in

limiting performance.

At very high input frequencies (> about 300 MHz), SFDR is determined largely by the device’s sampling circuit

non-linearity. At low input amplitudes, the quantizer non-linearity usually limits performance.

Glitches are caused by the opening and closing of the sampling switches. The driving circuit should present a

low source impedance to absorb these glitches. Otherwise, this could limit performance, mainly at low input

frequencies (up to about 200 MHz). It is also necessary to present low impedance (< 50

Ω) for the common

mode switching currents. This can be achieved by using two resistors from each input terminated to the common

mode voltage (VCM).

The device includes an internal R-C filter from each input to ground. The purpose of this filter is to absorb the

sampling glitches inside the device itself. The cut-off frequency of the R-C filter involves a trade-off.

A lower cut-off frequency (larger C) absorbs glitches better, but it reduces the input bandwidth. On the other

hand, with a higher cut-off frequency (smaller C), bandwidth support is maximized. But now, the sampling

glitches need to be supplied by the external drive circuit. This has limitations due to the presence of the package

bond-wire inductance.

In ADS58C48, the R-C component values have been optimized while supporting high input bandwidth (up to 550

MHz). However, in applications with input frequencies up to 200 - 300 MHz, the filtering of the glitches can be

improved further using an external R-C-R filter (as shown in Figure 54 and Figure 55).

In addition to the above, the drive circuit may have to be designed to provide a low insertion loss over the

desired frequency range and matched impedance to the source. While doing this, the ADC input impedance

must be considered. Figure 52 and Figure 53 show the impedance (Zin = Rin || Cin) looking into the ADC input

pins.

DIFFERENTIAL INPUT RESISTANCE

DIFFERENTIAL INPUT CAPACITANCE

FREQUENCY

Figure 52. ADC Analog Input Resistance (Rin)

Figure 53. ADC Analog Input Capacitance (Cin)

Across Frequency

Driving Circuit

Two example driving circuit configurations are shown in Figure 54 and Figure 55, one optimized for low

bandwidth (low input frequencies) and the other one for high bandwidth to support higher input frequencies.

Note that both the drive circuits have been terminated by 50

Ω near the ADC side. The termination is

accomplished by a 25-

Ω resistor from each input to the 1.5-V common-mode (VCM) from the device. This allows

the analog inputs to be biased around the required common-mode voltage.

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