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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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ADS58C48IPFPR датащи(PDF) 58 Page - Texas Instruments |
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ADS58C48IPFPR датащи(HTML) 58 Page - Texas Instruments |
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58 / 70 page  SAMPLEN CLKOUTP CLKOUTM SAMPLEN+1 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 CHA<0>,CHB<0> CHC<0>,CHD<0> D0 D0 0 0 CHA<2>,CHB<2> CHC<2>,CHD<2> CHA<4>,CHB<4> CHC<4>,CHD<4> CHA<6>,CHB<6> CHC<6>,CHD<6> CHA<8>,CHB<8> CHC<8>,CHD<8> CHA<10>,CHB<10> CHC<10>,CHD<10> ADS58C48 SLAS689 – MAY 2010 www.ti.com Figure 61. DDR LVDS Interface Timing Diagram LVDS Output Data and Clock Buffers The equivalent circuit of each LVDS output buffer is shown in Figure 62. After reset, the buffer presents an output impedance of 100 Ω to match with the external 100-Ω termination. The Vdiff voltage is nominally 350 mV, resulting in an output swing of ±350 mV with 100- Ω external termination. The Vdiff voltage is programmable using the register bits <LVDS SWING> from ±125 mV to ±570 mV. Additionally, a mode exists to double the strength of the LVDS buffer to support 50- Ω differential termination. This can be used when the output LVDS signal is routed to two separate receiver chips, each using a 100- Ω termination. The mode can be enabled using register bits <LVDS DATA STRENGTH> and <LVDS CLKOUT STRENGTH> for data and output clock buffers respectively. The buffer output impedance behaves like a source-side series termination. By absorbing reflections from the receiver end, it helps to improve signal integrity. 58 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s) :ADS58C48 |
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