ADS58C48IPFPR datasheet(8/70 Pages) TI

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ADS58C48

SLAS689 – MAY 2010

www.ti.com

TIMING CHARACTERISTICS – LVDS AND CMOS MODES

(1)

Typical values are at 25°C, AVDD = 1.8 V, DRVDD = 1.8 V, sampling frequency = 200 MSPS, sine wave input clock, CLOAD =

5 pF

(2), R

LOAD = 100 Ω

(3), unless otherwise noted.

MIN and MAX values are across the full temperature range TMIN = –40°C to TMAX = 85°C, AVDD = 1.8 V, DRVDD = 1.7 V to

1.9 V.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Aperture delay

0.5

0.8

1.1

Aperture delay matching

Between the 4 channels of the same device

±70

Variation of aperture delay

Between two devices at same temperature and

±150

DRVDD supply

Aperture jitter

140

fs rms

Wake-up time

Time to valid data after coming out of STANDBY

µs

mode

Time to valid data after coming out of GLOBAL

100

500

µs

power down mode

Time to valid data after stopping and restarting the

µs

input clock

ADC latency (4)

Default latency after reset, DIGITAL MODE1=0,

Clock

DIGITAL MODE2=0

cycles

SNRBoost only enabled, DIGITAL MODE1=0,

Clock

DIGITAL MODE2=1

cycles

SNRBoost, Gain and Offset corr enabled, DIGITAL

Clock

MODE1=1, DIGITAL MODE2=0 or 1

cycles

DDR LVDS MODE (5)

tsu

Data setup time(6)

Data valid(6) to zero-crossing of CLKOUTP

0.5

1.1

Data hold time(6)

Zero-crossing of CLKOUTP to data becoming

0.35

0.70

invalid(6)

tPDI

Clock propagation delay

Input clock rising edge cross-over to output clock

4.5

7.5

rising edge cross-over

1 MSPS ≤ Sampling frequency ≤ 200 MSPS

Variation of tPDI

Between two devices at same temperature and

±0.8

DRVDD supply

LVDS bit clock duty cycle

Duty cycle of differential clock,

45%

50%

55%

(CLKOUTP-CLKOUTM)

1 MSPS ≤ Sampling frequency ≤ 200 MSPS

tRISE,

Data rise time, Data fall time

Rise time measured from –100 mV to +100 mV

0.14

tFALL

Fall time measured from +100 mV to –100 mV

1MSPS ≤ Sampling frequency ≤ 200 MSPS

tCLKRISE,

Output clock rise time,

Rise time measured from –100 mV to +100 mV

0.18

tCLKFALL

Output clock fall time

Fall time measured from +100 mV to –100 mV

1 MSPS ≤ Sampling frequency ≤ 200 MSPS

PARALLEL CMOS MODE

tSTART

Input clock to data delay

Input clock falling edge cross-over to start of data

–0.40

valid(7)

tDV

Data valid time

Time interval of data valid(7)

3.2

3.8

Output clock duty cycle

Duty cycle of output clock, CLKOUT

45%

1 MSPS ≤ Sampling frequency ≤ 150 MSPS

tRISE ,

Data rise time,

Rise time measured from 20% to 80% of DRVDD

0.6

tFALL

Data fall time

Fall time measured from 80% to 20% of DRVDD

1 ≤ Sampling frequency ≤ 200 MSPS

(1)

Timing parameters are ensured by design and characterization and not tested in production.

(2)

CLOAD is the effective external single-ended load capacitance between each output pin and ground

(3)

RLOAD is the differential load resistance between the LVDS output pair.

(4)

At higher frequencies, tPDI is greater than one clock period and overall latency = ADC latency + 1.

(5)

Measurements are done with a transmission line of 100-

Ω characteristic impedance between the device and the load. Setup and hold

time specifications take into account the effect of jitter on the output data and clock.

(6)

Data valid refers to LOGIC HIGH of +100.0 mV and LOGIC LOW of –100.0 mV.

(7)

Data valid refers to LOGIC HIGH of 1.26 V and LOGIC LOW of 0.54 V

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