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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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H838532H датащи(PDF) 145 Page - Renesas Technology Corp |
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H838532H датащи(HTML) 145 Page - Renesas Technology Corp |
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145 / 508 page  Section 6 ROM Rev. 1.00 May 30, 2008 Page 125 of 484 REJ09B0436-0100 6.2.4 Register Configuration Table 6.1 lists the register configuration to control the flash memory when the built in flash memory is effective. Table 6.1 Register Configuration Register Name Abbreviation R/W Initial Value Address Flash memory control register 1 FLMCR1 R/W H'00 H'F020 Flash memory control register 2 FLMCR2 R H'00 H'F021 Flash memory power control register FLPWCR R/W H'00 H'F022 Erase block register EBR R/W H'00 H'F023 Flash memory enable register FENR R/W H'00 H'F02B Note: FLMCR1, FLMCR2, FLPWCR, EBR, and FENR are 8 bit registers. Only byte access is enabled which are two-state access. These registers are dedicated to the product in which flash memory is included. The product in which mask ROM is included does not have these registers. When the corresponding address is read in these products, the value is undefined. A write is disabled. |
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