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H838532H датащи(PDF) 142 Page - Renesas Technology Corp |
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H838532H датащи(HTML) 142 Page - Renesas Technology Corp |
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142 / 508 page ![]() Section 6 ROM Rev. 1.00 May 30, 2008 Page 122 of 484 REJ09B0436-0100 • Programming/erasing protection Sets software protection against flash memory programming/erasing. • Power-down mode The power supply circuit is partly halted in the subactive mode and can be read in the power-down mode. 6.2.2 Block Diagram Internal address bus Internal data bus (16 bits) FLMCR1 Bus interface/controller Operating mode TES pin P32 pin P86 pin Legend: FLMCR1: Flash memory control register 1 FLMCR2: Flash memory control register 2 EBR: Erase block register FLPWCR: Flash memory power control register FENR: Flash memory enable register FLMCR2 EBR FLPWCR FENR Flash memory Figure 6.1 Block Diagram of Flash Memory |
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