H838532H datasheet(136/508 Pages) RENESAS

136 / 508 page

Section 5 Power-Down Modes

Rev. 1.00 May 30, 2008 Page 116 of 484

REJ09B0436-0100

The time from execution of the SLEEP instruction to the end of interrupt exception handling (the

direct transition time) is given by equation (2) below.

Direct transition time = { (Number of SLEEP instruction execution states) + (number of internal

processing states) }

× (tcyc before transition) + (number of interrupt

exception handling execution states)

× (tcyc after transition)

.................................. (2)

Example: Direct transition time = (2 + 1)

× 16tosc + 14 × 2tosc = 76tosc (when φ/8 is selected as

the CPU operating clock)

Notation:

tosc: OSC clock cycle time

tcyc: System clock (

φ) cycle time

(3) Time for Direct Transition from Subactive Mode to Active (High-Speed) Mode

A direct transition from subactive mode to active (high-speed) mode is performed by executing a

SLEEP instruction in subactive mode while bit SSBY is set to 1 and bit LSON is cleared to 0 in

SYSCR1, bit MSON is cleared to 0 and bit DTON is set to 1 in SYSCR2, and bit TMA3 is set to 1

in TMA. The time from execution of the SLEEP instruction to the end of interrupt exception

handling (the direct transition time) is given by equation (3) below.

Direct transition time = { (Number of SLEEP instruction execution states) + (number of internal

processing states) }

× (tsubcyc before transition) + { (wait time set in

STS2 to STS0) + (number of interrupt exception handling execution

states) }

× (tcyc after transition)

........................ (3)

Example: Direct transition time = (2 + 1)

× 8tw + (8192 + 14) × 2tosc = 24tw + 16412tosc (when

φw/8 is selected as the CPU operating clock, and wait time = 8192 states)

Notation:

tosc:

OSC clock cycle time

tw:

Watch clock cycle time

tcyc:

System clock (

φ) cycle time

tsubcyc: Subclock (

SUB) cycle time

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